BR9905641A - Loop de bloqueio de fase e método decorrente - Google Patents

Loop de bloqueio de fase e método decorrente

Info

Publication number
BR9905641A
BR9905641A BR9905641-0A BR9905641A BR9905641A BR 9905641 A BR9905641 A BR 9905641A BR 9905641 A BR9905641 A BR 9905641A BR 9905641 A BR9905641 A BR 9905641A
Authority
BR
Brazil
Prior art keywords
divider
vco
pll
receive
modulation
Prior art date
Application number
BR9905641-0A
Other languages
English (en)
Inventor
Gregory Redmond Black
Louis Michael Nigra
Michael Edward Denzin
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of BR9905641A publication Critical patent/BR9905641A/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C3/00—Angle modulation
    • H03C3/02—Details
    • H03C3/09—Modifications of modulator for regulating the mean frequency
    • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
    • H03C3/0991—Modifications of modulator for regulating the mean frequency using a phase locked loop including calibration means or calibration methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C3/00—Angle modulation
    • H03C3/02—Details
    • H03C3/09—Modifications of modulator for regulating the mean frequency
    • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
    • H03C3/0916—Modifications of modulator for regulating the mean frequency using a phase locked loop with frequency divider or counter in the loop
    • H03C3/0925—Modifications of modulator for regulating the mean frequency using a phase locked loop with frequency divider or counter in the loop applying frequency modulation at the divider in the feedback loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C3/00—Angle modulation
    • H03C3/02—Details
    • H03C3/09—Modifications of modulator for regulating the mean frequency
    • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
    • H03C3/0941—Modifications of modulator for regulating the mean frequency using a phase locked loop applying frequency modulation at more than one point in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C3/00—Angle modulation
    • H03C3/02—Details
    • H03C3/09—Modifications of modulator for regulating the mean frequency
    • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
    • H03C3/0966—Modifications of modulator for regulating the mean frequency using a phase locked loop modulating the reference clock
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Transmitters (AREA)

Abstract

<B>LOOP DE BLOQUEIO DE FASE E MéTODO DECORRENTE<D> Um loop de bloqueio de fase (PLL) de modulação direta, um oscilador controlado por tensão (VCO - 114). Um divisor (118) que tem uma primeira entrada de divisor acoplada ao VCO, e uma segunda entrada de divisor para receber uma seq³ência divisora de indução de modulação. Um detetor de fase (102) que tem uma primeira entrada de detetor acoplada ao divisor para receber a saída deste, e uma segunda entrada de detetor para receber uma entrada de referência. Um circuito de sintonia (306 e 406) é acoplado ao detetor de fase e ao VCO, o circuito de sintonia responsivo a um potencial de referência de DC variável de forma que o circuito de sintonia tenha uma resposta de freq³ência que seja constante sobre a largura da faixa de modulação pela qual o PLL é um PLL do tipo I com baixa distorção de modulação.
BR9905641-0A 1998-11-23 1999-11-18 Loop de bloqueio de fase e método decorrente BR9905641A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/197,986 US6157271A (en) 1998-11-23 1998-11-23 Rapid tuning, low distortion digital direct modulation phase locked loop and method therefor

Publications (1)

Publication Number Publication Date
BR9905641A true BR9905641A (pt) 2000-10-03

Family

ID=22731539

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9905641-0A BR9905641A (pt) 1998-11-23 1999-11-18 Loop de bloqueio de fase e método decorrente

Country Status (7)

Country Link
US (1) US6157271A (pt)
JP (1) JP2000165459A (pt)
KR (1) KR20000035604A (pt)
CN (1) CN1255782A (pt)
BR (1) BR9905641A (pt)
DE (1) DE19954255B4 (pt)
GB (1) GB2344006B (pt)

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US6339368B1 (en) * 2000-03-31 2002-01-15 Zilog, Inc. Circuit for automatically driving mechanical device at its resonance frequency
US6396355B1 (en) * 2000-04-12 2002-05-28 Rockwell Collins, Inc. Signal generator having fine resolution and low phase noise
US6664826B1 (en) * 2000-07-20 2003-12-16 Motorola, Inc. Loop filter and amplifier for improved phase margin and decreased phase noise with VCOs
US6851493B2 (en) * 2000-12-01 2005-02-08 Texas Instruments Incorporated Digital PLL with gear shift
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GB0104535D0 (en) * 2001-02-23 2001-04-11 Univ Bristol Digital cartesian loop
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US6680654B2 (en) * 2001-10-24 2004-01-20 Northrop Grumman Corporation Phase locked loop with offset cancellation
US6717475B2 (en) * 2001-11-01 2004-04-06 Skyworks Solutions, Inc. Fast-acquisition phase-locked loop
US6728651B1 (en) * 2002-03-13 2004-04-27 Ltx Corporation Methods and apparatuses for digitally tuning a phased-lock loop circuit
DE10242364A1 (de) 2002-09-12 2004-03-25 Infineon Technologies Ag Phasenregelkreis
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Also Published As

Publication number Publication date
KR20000035604A (ko) 2000-06-26
GB2344006A (en) 2000-05-24
GB2344006B (en) 2001-01-17
GB9926094D0 (en) 2000-01-12
US6157271A (en) 2000-12-05
CN1255782A (zh) 2000-06-07
DE19954255B4 (de) 2004-09-30
DE19954255A1 (de) 2000-06-08
JP2000165459A (ja) 2000-06-16

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 3A,4A,5A,6A,7 E 8A ANUIDADES

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 1910 DE 14/08/2007.