BR8406284A - Sistema de adicao/subtracao com virgula flutuante para duas series de dados - Google Patents

Sistema de adicao/subtracao com virgula flutuante para duas series de dados

Info

Publication number
BR8406284A
BR8406284A BR8406284A BR8406284A BR8406284A BR 8406284 A BR8406284 A BR 8406284A BR 8406284 A BR8406284 A BR 8406284A BR 8406284 A BR8406284 A BR 8406284A BR 8406284 A BR8406284 A BR 8406284A
Authority
BR
Brazil
Prior art keywords
additional
floating point
data series
subtraction system
subtraction
Prior art date
Application number
BR8406284A
Other languages
English (en)
Inventor
Masayuki Ikeda
Kohichi Ueda
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP58233114A external-priority patent/JPS60124729A/ja
Priority claimed from JP58248422A external-priority patent/JPS60142736A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of BR8406284A publication Critical patent/BR8406284A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/485—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49936—Normalisation mentioned as feature only

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Complex Calculations (AREA)
  • Image Processing (AREA)
BR8406284A 1983-12-09 1984-12-07 Sistema de adicao/subtracao com virgula flutuante para duas series de dados BR8406284A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP58233114A JPS60124729A (ja) 1983-12-09 1983-12-09 浮動小数点加減算方式
JP58248422A JPS60142736A (ja) 1983-12-29 1983-12-29 浮動小数点加減算方式

Publications (1)

Publication Number Publication Date
BR8406284A true BR8406284A (pt) 1985-10-01

Family

ID=26530854

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8406284A BR8406284A (pt) 1983-12-09 1984-12-07 Sistema de adicao/subtracao com virgula flutuante para duas series de dados

Country Status (8)

Country Link
US (1) US5016209A (pt)
EP (1) EP0145465B1 (pt)
KR (1) KR890004307B1 (pt)
AU (1) AU555230B2 (pt)
BR (1) BR8406284A (pt)
CA (1) CA1229415A (pt)
DE (1) DE3481788D1 (pt)
ES (1) ES8602270A1 (pt)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3236391C2 (de) * 1982-10-01 1992-05-27 Hans Joachim Dipl.-Ing. Eitel Gießpulver für den Stahlguß
US4760550A (en) * 1986-09-11 1988-07-26 Amdahl Corporation Saving cycles in floating point division
US4858165A (en) * 1987-06-19 1989-08-15 Digital Equipment Corporation Apparatus and method for acceleration of effective subtraction procedures by the approximation of the absolute value of the exponent argument difference
JP2695178B2 (ja) * 1988-03-11 1997-12-24 富士通株式会社 演算回路
CA2050799C (en) * 1990-09-07 1994-03-22 Shingo Ishihara Shift amount floating-point calculating circuit with a small amount of hardware and rapidly operable
US5247471A (en) * 1991-12-13 1993-09-21 International Business Machines Corporation Radix aligner for floating point addition and subtraction
KR970016936A (ko) * 1995-09-06 1997-04-28 엘리 와이스 최상위 디지트를 결정하는 장치 및 방법
US5901076A (en) * 1997-04-16 1999-05-04 Advanced Micro Designs, Inc. Ripple carry shifter in a floating point arithmetic unit of a microprocessor
US6148315A (en) * 1998-04-30 2000-11-14 Mentor Graphics Corporation Floating point unit having a unified adder-shifter design
JP3609307B2 (ja) * 1999-12-07 2005-01-12 シャープ株式会社 文書管理装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3551665A (en) * 1966-09-13 1970-12-29 Ibm Floating point binary adder utilizing completely sequential hardware
JPS5776635A (en) * 1980-10-31 1982-05-13 Hitachi Ltd Floating multiplying circuit
US4488252A (en) * 1982-02-22 1984-12-11 Raytheon Company Floating point addition architecture
US4562553A (en) * 1984-03-19 1985-12-31 Analogic Corporation Floating point arithmetic system and method with rounding anticipation

Also Published As

Publication number Publication date
US5016209A (en) 1991-05-14
KR850004818A (ko) 1985-07-27
AU555230B2 (en) 1986-09-18
EP0145465B1 (en) 1990-03-28
ES538377A0 (es) 1985-11-01
AU3627084A (en) 1985-06-13
CA1229415A (en) 1987-11-17
ES8602270A1 (es) 1985-11-01
EP0145465A2 (en) 1985-06-19
DE3481788D1 (de) 1990-05-03
EP0145465A3 (en) 1986-05-28
KR890004307B1 (ko) 1989-10-30

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Legal Events

Date Code Title Description
B21A Patent or certificate of addition expired [chapter 21.1 patent gazette]

Free format text: PATENTE EXTINTA EM 07/12/99