BR8304954A - Sistema de processamento de dados - Google Patents

Sistema de processamento de dados

Info

Publication number
BR8304954A
BR8304954A BR8304954A BR8304954A BR8304954A BR 8304954 A BR8304954 A BR 8304954A BR 8304954 A BR8304954 A BR 8304954A BR 8304954 A BR8304954 A BR 8304954A BR 8304954 A BR8304954 A BR 8304954A
Authority
BR
Brazil
Prior art keywords
data processing
processing system
data
processing
Prior art date
Application number
BR8304954A
Other languages
English (en)
Inventor
Yoshiaki Matsubara
Masato Tsuru
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of BR8304954A publication Critical patent/BR8304954A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bus Control (AREA)
BR8304954A 1982-09-13 1983-09-13 Sistema de processamento de dados BR8304954A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57159103A JPS5947625A (ja) 1982-09-13 1982-09-13 入出力割り込み方式

Publications (1)

Publication Number Publication Date
BR8304954A true BR8304954A (pt) 1984-04-24

Family

ID=15686300

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8304954A BR8304954A (pt) 1982-09-13 1983-09-13 Sistema de processamento de dados

Country Status (8)

Country Link
US (1) US4644462A (pt)
EP (1) EP0106498B1 (pt)
JP (1) JPS5947625A (pt)
AU (1) AU544391B2 (pt)
BR (1) BR8304954A (pt)
CA (1) CA1200912A (pt)
DE (1) DE3380323D1 (pt)
ES (1) ES525537A0 (pt)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63123218A (ja) * 1986-11-12 1988-05-27 Nec Corp タイマ／カウンタ回路
JPH0776951B2 (ja) * 1990-10-30 1995-08-16 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュータシステム、複数の入出力アダプタによるアドレス空間共用システム、及び複数の入出力装置とコンピュータプロセッサ間の通信管理方
US5542076A (en) * 1991-06-14 1996-07-30 Digital Equipment Corporation Method and apparatus for adaptive interrupt servicing in data processing system
US5414814A (en) * 1992-05-08 1995-05-09 The United States Of America As Represented By The Secretary Of The Navy I/O interface between VME bus and asynchronous serial data computer
US5581770A (en) * 1992-06-04 1996-12-03 Mitsubishi Denki Kabushiki Kaisha Floating interruption handling system and method
US5313640A (en) * 1992-09-23 1994-05-17 International Business Machines Corporation Method and system for the efficient response to multiple different types of interrupts
JPH06100998B2 (ja) * 1992-10-02 1994-12-12 インターナショナル・ビジネス・マシーンズ・コーポレイション データ転送制御用インターフェース回路
JP3474646B2 (ja) * 1994-09-01 2003-12-08 富士通株式会社 入出力制御装置及び入出力制御方法
US5748855A (en) * 1995-10-02 1998-05-05 Iinternational Business Machines Corporation Method and system for performance monitoring of misaligned memory accesses in a processing system
US5751945A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring stalls to identify pipeline bottlenecks and stalls in a processing system
US5752062A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring through monitoring an order of processor events during execution in a processing system
US5691920A (en) * 1995-10-02 1997-11-25 International Business Machines Corporation Method and system for performance monitoring of dispatch unit efficiency in a processing system
US5797019A (en) * 1995-10-02 1998-08-18 International Business Machines Corporation Method and system for performance monitoring time lengths of disabled interrupts in a processing system
US5949971A (en) * 1995-10-02 1999-09-07 International Business Machines Corporation Method and system for performance monitoring through identification of frequency and length of time of execution of serialization instructions in a processing system
US5729726A (en) * 1995-10-02 1998-03-17 International Business Machines Corporation Method and system for performance monitoring efficiency of branch unit operation in a processing system
US5987537A (en) * 1997-04-30 1999-11-16 Compaq Computer Corporation Function selector with external hard wired button array on computer chassis that generates interrupt to system processor
USRE42761E1 (en) 1997-12-31 2011-09-27 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
US5941972A (en) 1997-12-31 1999-08-24 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
US20100154304A1 (en) * 2007-07-17 2010-06-24 Plasco Energy Group Inc. Gasifier comprising one or more fluid conduits

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4056843A (en) * 1976-06-07 1977-11-01 Amdahl Corporation Data processing system having a plurality of channel processors
US4348725A (en) * 1977-01-19 1982-09-07 Honeywell Information Systems Inc. Communication line service interrupt technique for a communications processing system
US4207609A (en) * 1978-05-08 1980-06-10 International Business Machines Corporation Method and means for path independent device reservation and reconnection in a multi-CPU and shared device access system
US4400773A (en) * 1980-12-31 1983-08-23 International Business Machines Corp. Independent handling of I/O interrupt requests and associated status information transfers

Also Published As

Publication number Publication date
DE3380323D1 (en) 1989-09-07
ES8405970A1 (es) 1984-06-16
EP0106498A2 (en) 1984-04-25
CA1200912A (en) 1986-02-18
EP0106498B1 (en) 1989-08-02
EP0106498A3 (en) 1985-11-13
JPS5947625A (ja) 1984-03-17
AU1874483A (en) 1984-03-22
US4644462A (en) 1987-02-17
AU544391B2 (en) 1985-05-23
JPS61662B2 (pt) 1986-01-10
ES525537A0 (es) 1984-06-16

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Legal Events

Date Code Title Description
MM Lapse due to non-payment of fees (art. 50)