ES552464A0 - Sistema de proceso de datos - Google Patents

Sistema de proceso de datos

Info

Publication number
ES552464A0
ES552464A0 ES552464A ES552464A ES552464A0 ES 552464 A0 ES552464 A0 ES 552464A0 ES 552464 A ES552464 A ES 552464A ES 552464 A ES552464 A ES 552464A ES 552464 A0 ES552464 A0 ES 552464A0
Authority
ES
Spain
Prior art keywords
data processing
processing system
data
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES552464A
Other languages
English (en)
Other versions
ES8706986A1 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES8706986A1 publication Critical patent/ES8706986A1/es
Publication of ES552464A0 publication Critical patent/ES552464A0/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
ES552464A 1985-02-28 1986-02-27 Sistema de proceso de datos Expired ES8706986A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/706,802 US4695945A (en) 1985-02-28 1985-02-28 Processor I/O and interrupt filters allowing a co-processor to run software unknown to the main processor

Publications (2)

Publication Number Publication Date
ES8706986A1 ES8706986A1 (es) 1987-07-01
ES552464A0 true ES552464A0 (es) 1987-07-01

Family

ID=24839100

Family Applications (1)

Application Number Title Priority Date Filing Date
ES552464A Expired ES8706986A1 (es) 1985-02-28 1986-02-27 Sistema de proceso de datos

Country Status (15)

Country Link
US (1) US4695945A (es)
EP (1) EP0192944B1 (es)
JP (1) JPS61202269A (es)
KR (1) KR900006549B1 (es)
CN (1) CN1008484B (es)
BR (1) BR8600665A (es)
CA (1) CA1236582A (es)
DE (1) DE3689696T2 (es)
ES (1) ES8706986A1 (es)
GB (1) GB2171823B (es)
HK (1) HK19190A (es)
IN (1) IN166350B (es)
MY (1) MY101469A (es)
PH (1) PH23471A (es)
SG (1) SG61789G (es)

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US5146565A (en) * 1986-07-18 1992-09-08 Intel Corporation I/O Control system having a plurality of access enabling bits for controlling access to selective ports of an I/O device
US5257353A (en) * 1986-07-18 1993-10-26 Intel Corporation I/O control system having a plurality of access enabling bits for controlling access to selective parts of an I/O device
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US5226122A (en) * 1987-08-21 1993-07-06 Compaq Computer Corp. Programmable logic system for filtering commands to a microprocessor
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IL88165A (en) * 1987-12-21 1993-01-31 Honeywell Bull Apparatus and method for a data processing system having a peer relationship among a plurality of central processing units
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US5027271A (en) * 1987-12-21 1991-06-25 Bull Hn Information Systems Inc. Apparatus and method for alterable resource partitioning enforcement in a data processing system having central processing units using different operating systems
US5129064A (en) * 1988-02-01 1992-07-07 International Business Machines Corporation System and method for simulating the I/O of a processing system
US4912628A (en) * 1988-03-15 1990-03-27 International Business Machines Corp. Suspending and resuming processing of tasks running in a virtual machine data processing system
US5032982A (en) * 1988-05-18 1991-07-16 Zilog, Inc. Device for timing interrupt acknowledge cycles
JPH01297764A (ja) * 1988-05-25 1989-11-30 Nec Corp プロセッサ
US5101497A (en) * 1988-09-09 1992-03-31 Compaq Computer Corporation Programmable interrupt controller
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JPH02129753A (ja) * 1988-11-10 1990-05-17 Fuji Electric Co Ltd マルチプロセッサシステム
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CA2009780C (en) * 1989-05-17 1999-07-27 Ernest D. Baker Method and apparatus for the direct transfer of information between application programs running on distinct processors without utilizing the services of one or both operating systems
US5155809A (en) * 1989-05-17 1992-10-13 International Business Machines Corp. Uncoupling a central processing unit from its associated hardware for interaction with data handling apparatus alien to the operating system controlling said unit and hardware
US5369767A (en) * 1989-05-17 1994-11-29 International Business Machines Corp. Servicing interrupt requests in a data processing system without using the services of an operating system
US5077657A (en) * 1989-06-15 1991-12-31 Unisys Emulator Assist unit which forms addresses of user instruction operands in response to emulator assist unit commands from host processor
CA2026770A1 (en) * 1989-11-03 1991-05-04 John A. Landry Multiprocessor interrupt control
US5247685A (en) * 1989-11-03 1993-09-21 Compaq Computer Corp. Interrupt handling in an asymmetric multiprocessor computer system
JPH03210652A (ja) * 1989-11-09 1991-09-13 Internatl Business Mach Corp <Ibm> 透過アクセス方法及び装置
US5170266A (en) * 1990-02-20 1992-12-08 Document Technologies, Inc. Multi-capability facsimile system
AU9043691A (en) * 1990-11-09 1992-06-11 Ast Research, Inc. Protected hot key function for microprocessor-based computer system
EP0974912B1 (en) * 1993-12-01 2008-11-05 Marathon Technologies Corporation Fault resilient/fault tolerant computing
AU1989395A (en) * 1994-03-14 1995-10-03 Apple Computer, Inc. A peripheral processor card for upgrading a computer
US5640592A (en) * 1994-09-30 1997-06-17 Mitsubishi Kasei America, Inc. System for transferring utility algorithm stored within a peripheral device to a host computer in a format compatible with the type of the host computer
US5574920A (en) * 1994-10-25 1996-11-12 Microsoft Corporation Method for controlling power down of a hard disk drive in a computer
FR2726383A1 (fr) * 1994-10-26 1996-05-03 Trt Telecom Radio Electr Systeme de traitement d'informations comportant au moins deux processeurs
US5732279A (en) * 1994-11-10 1998-03-24 Brooktree Corporation System and method for command processing or emulation in a computer system using interrupts, such as emulation of DMA commands using burst mode data transfer for sound or the like
US5790397A (en) * 1996-09-17 1998-08-04 Marathon Technologies Corporation Fault resilient/fault tolerant computing
US6145030A (en) * 1998-03-27 2000-11-07 Intel Corporation System for managing input/output address accesses at a bridge/memory controller
US6526514B1 (en) * 1999-10-11 2003-02-25 Ati International Srl Method and apparatus for power management interrupt processing in a computing system
JP3621315B2 (ja) * 1999-11-22 2005-02-16 Ｎｅｃエレクトロニクス株式会社 マイクロプロセッサシステム
US6772241B1 (en) 2000-09-29 2004-08-03 Intel Corporation Selective interrupt delivery to multiple processors having independent operating systems
US7302462B2 (en) * 2001-03-12 2007-11-27 Mercury Computer Systems, Inc. Framework and methods for dynamic execution of digital data processor resources
CN100377093C (zh) * 2006-04-07 2008-03-26 浙江大学 嵌入式操作系统输入输出设备软件化方法
TWI324304B (en) * 2006-12-15 2010-05-01 Inventec Corp Method for reading data of input/output port
US7958183B2 (en) 2007-08-27 2011-06-07 International Business Machines Corporation Performing collective operations using software setup and partial software execution at leaf nodes in a multi-tiered full-graph interconnect architecture
US7840703B2 (en) 2007-08-27 2010-11-23 International Business Machines Corporation System and method for dynamically supporting indirect routing within a multi-tiered full-graph interconnect architecture
US7793158B2 (en) 2007-08-27 2010-09-07 International Business Machines Corporation Providing reliability of communication between supernodes of a multi-tiered full-graph interconnect architecture
US8140731B2 (en) 2007-08-27 2012-03-20 International Business Machines Corporation System for data processing using a multi-tiered full-graph interconnect architecture
US7904590B2 (en) 2007-08-27 2011-03-08 International Business Machines Corporation Routing information through a data processing system implementing a multi-tiered full-graph interconnect architecture
US8185896B2 (en) 2007-08-27 2012-05-22 International Business Machines Corporation Method for data processing using a multi-tiered full-graph interconnect architecture
US7769891B2 (en) 2007-08-27 2010-08-03 International Business Machines Corporation System and method for providing multiple redundant direct routes between supernodes of a multi-tiered full-graph interconnect architecture
US7822889B2 (en) 2007-08-27 2010-10-26 International Business Machines Corporation Direct/indirect transmission of information using a multi-tiered full-graph interconnect architecture
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US8014387B2 (en) 2007-08-27 2011-09-06 International Business Machines Corporation Providing a fully non-blocking switch in a supernode of a multi-tiered full-graph interconnect architecture
US7809970B2 (en) 2007-08-27 2010-10-05 International Business Machines Corporation System and method for providing a high-speed message passing interface for barrier operations in a multi-tiered full-graph interconnect architecture
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US7827428B2 (en) 2007-08-31 2010-11-02 International Business Machines Corporation System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture
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US20090198956A1 (en) * 2008-02-01 2009-08-06 Arimilli Lakshminarayana B System and Method for Data Processing Using a Low-Cost Two-Tier Full-Graph Interconnect Architecture
US8077602B2 (en) 2008-02-01 2011-12-13 International Business Machines Corporation Performing dynamic request routing based on broadcast queue depths
US8417778B2 (en) * 2009-12-17 2013-04-09 International Business Machines Corporation Collective acceleration unit tree flow control and retransmit
US8751655B2 (en) 2010-03-29 2014-06-10 International Business Machines Corporation Collective acceleration unit tree structure
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US8661177B2 (en) * 2011-12-19 2014-02-25 Advanced Micro Devices, Inc. Method and apparatus for controlling system interrupts
US9690725B2 (en) 2014-01-14 2017-06-27 Qualcomm Incorporated Camera control interface extension with in-band interrupt
US10353837B2 (en) 2013-09-09 2019-07-16 Qualcomm Incorporated Method and apparatus to enable multiple masters to operate in a single master bus architecture
US9996488B2 (en) 2013-09-09 2018-06-12 Qualcomm Incorporated I3C high data rate (HDR) always-on image sensor 8-bit operation indicator and buffer over threshold indicator
US9519603B2 (en) * 2013-09-09 2016-12-13 Qualcomm Incorporated Method and apparatus to enable multiple masters to operate in a single master bus architecture
KR20160070171A (ko) 2013-10-09 2016-06-17 퀄컴 인코포레이티드 CCIe 프로토콜을 통한 에러 검출 능력
US9684624B2 (en) 2014-01-14 2017-06-20 Qualcomm Incorporated Receive clock calibration for a serial bus
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US4695945A (en) * 1985-02-28 1987-09-22 International Business Machines Corporation Processor I/O and interrupt filters allowing a co-processor to run software unknown to the main processor

Also Published As

Publication number Publication date
EP0192944A2 (en) 1986-09-03
IN166350B (es) 1990-04-14
EP0192944A3 (en) 1989-04-19
MY101469A (en) 1991-11-18
CA1236582A (en) 1988-05-10
CN86100690A (zh) 1986-08-27
BR8600665A (pt) 1986-10-29
GB8525990D0 (en) 1985-11-27
ES8706986A1 (es) 1987-07-01
SG61789G (en) 1990-03-09
KR900006549B1 (ko) 1990-09-13
CN1008484B (zh) 1990-06-20
DE3689696T2 (de) 1994-09-22
JPH0221018B2 (es) 1990-05-11
DE3689696D1 (de) 1994-04-14
US4695945A (en) 1987-09-22
EP0192944B1 (en) 1994-03-09
KR860006743A (ko) 1986-09-15
PH23471A (en) 1989-08-07
JPS61202269A (ja) 1986-09-08
GB2171823A (en) 1986-09-03
HK19190A (en) 1990-03-23
GB2171823B (en) 1989-06-14

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