BR112023020878A2 - Múltiplos blocos de funções em um sistema em um chip (soc) - Google Patents

Múltiplos blocos de funções em um sistema em um chip (soc)

Info

Publication number
BR112023020878A2
BR112023020878A2 BR112023020878A BR112023020878A BR112023020878A2 BR 112023020878 A2 BR112023020878 A2 BR 112023020878A2 BR 112023020878 A BR112023020878 A BR 112023020878A BR 112023020878 A BR112023020878 A BR 112023020878A BR 112023020878 A2 BR112023020878 A2 BR 112023020878A2
Authority
BR
Brazil
Prior art keywords
soc
dielectric layer
chip
function blocks
function block
Prior art date
Application number
BR112023020878A
Other languages
English (en)
Portuguese (pt)
Inventor
Giridhar Nallapati
Jianhong Zhu John
Junjing Bao
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112023020878A2 publication Critical patent/BR112023020878A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H10W20/0633—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material using subtractive patterning of the conductive members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/092—Manufacture or treatment of dielectric parts thereof by smoothing the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
BR112023020878A 2021-04-19 2022-03-24 Múltiplos blocos de funções em um sistema em um chip (soc) BR112023020878A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/234,377 US20220336351A1 (en) 2021-04-19 2021-04-19 Multiple function blocks on a system on a chip (soc)
PCT/US2022/071320 WO2022226458A1 (en) 2021-04-19 2022-03-24 Multiple function blocks on a system on a chip (soc)

Publications (1)

Publication Number Publication Date
BR112023020878A2 true BR112023020878A2 (pt) 2023-12-12

Family

ID=81307837

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112023020878A BR112023020878A2 (pt) 2021-04-19 2022-03-24 Múltiplos blocos de funções em um sistema em um chip (soc)

Country Status (7)

Country Link
US (1) US20220336351A1 (enExample)
EP (1) EP4327356A1 (enExample)
JP (1) JP2024516123A (enExample)
KR (1) KR20230173662A (enExample)
CN (1) CN117157745A (enExample)
BR (1) BR112023020878A2 (enExample)
WO (1) WO2022226458A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230031274A1 (en) * 2021-07-28 2023-02-02 Nanya Technology Corporation Semiconductor device structure with conductive contacts of different widths and method for preparing the same
CN115706081A (zh) * 2021-08-16 2023-02-17 联华电子股份有限公司 半导体结构及其制作方法
US20250349711A1 (en) * 2024-05-09 2025-11-13 International Business Machines Corporation Resistance and capacitance tuning in beol regions

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6720660B1 (en) * 1998-12-22 2004-04-13 Seiko Epson Corporation Semiconductor device and method for manufacturing the same
JP2000188332A (ja) * 1998-12-22 2000-07-04 Seiko Epson Corp 半導体装置及びその製造方法
KR100463895B1 (ko) * 2002-12-31 2004-12-30 엘지.필립스 엘시디 주식회사 콘택홀 형성방법
DE102005041283B4 (de) * 2005-08-31 2017-12-14 Globalfoundries Inc. Verfahren und Halbleiterstruktur zur Überwachung der Herstellung von Verbindungsstrukturen und Kontakten in einem Halbleiterbauelement
DE102008016431B4 (de) * 2008-03-31 2010-06-02 Advanced Micro Devices, Inc., Sunnyvale Metalldeckschicht mit erhöhtem Elektrodenpotential für kupferbasierte Metallgebiete in Halbleiterbauelementen sowie Verfahren zu ihrer Herstellung
JP5601974B2 (ja) * 2010-01-19 2014-10-08 パナソニック株式会社 半導体装置及びその製造方法
WO2012098759A1 (ja) * 2011-01-17 2012-07-26 住友電気工業株式会社 炭化珪素半導体装置の製造方法
KR101883379B1 (ko) * 2012-06-08 2018-07-30 삼성전자주식회사 반도체 장치
US9293412B2 (en) * 2012-12-17 2016-03-22 International Business Machines Corporation Graphene and metal interconnects with reduced contact resistance
US8778794B1 (en) * 2012-12-21 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnection wires of semiconductor devices
US9070644B2 (en) * 2013-03-15 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging mechanisms for dies with different sizes of connectors
US9105636B2 (en) * 2013-08-26 2015-08-11 Micron Technology, Inc. Semiconductor constructions and methods of forming electrically conductive contacts
US9564361B2 (en) * 2013-09-13 2017-02-07 Qualcomm Incorporated Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device
US10043703B2 (en) * 2016-12-15 2018-08-07 Globalfoundries Inc. Apparatus and method for forming interconnection lines having variable pitch and variable widths
US10541205B1 (en) * 2017-02-14 2020-01-21 Intel Corporation Manufacture of interconnects for integration of multiple integrated circuits
US10381305B2 (en) * 2017-08-29 2019-08-13 Micron Technology, Inc. Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch, and methods of forming integrated assemblies
US10534888B2 (en) * 2018-01-03 2020-01-14 International Business Machines Corporation Hybrid back end of line metallization to balance performance and reliability
US10586767B2 (en) * 2018-07-19 2020-03-10 International Business Machines Corporation Hybrid BEOL metallization utilizing selective reflection mask
US20200098692A1 (en) * 2018-09-26 2020-03-26 Intel Corporation Microelectronic assemblies having non-rectilinear arrangements
US10790162B2 (en) * 2018-09-27 2020-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11164825B2 (en) * 2018-10-31 2021-11-02 Taiwan Semiconductor Manufacturing Co., Ltd. CoWos interposer with selectable/programmable capacitance arrays
US11942334B2 (en) * 2018-12-21 2024-03-26 Intel Corporation Microelectronic assemblies having conductive structures with different thicknesses

Also Published As

Publication number Publication date
JP2024516123A (ja) 2024-04-12
WO2022226458A1 (en) 2022-10-27
US20220336351A1 (en) 2022-10-20
CN117157745A (zh) 2023-12-01
EP4327356A1 (en) 2024-02-28
TW202245213A (zh) 2022-11-16
KR20230173662A (ko) 2023-12-27

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