BR112023013292A2 - Substrato compreendendo interconexões em uma camada de núcleo configurada para correspondência de skew - Google Patents

Substrato compreendendo interconexões em uma camada de núcleo configurada para correspondência de skew

Info

Publication number
BR112023013292A2
BR112023013292A2 BR112023013292A BR112023013292A BR112023013292A2 BR 112023013292 A2 BR112023013292 A2 BR 112023013292A2 BR 112023013292 A BR112023013292 A BR 112023013292A BR 112023013292 A BR112023013292 A BR 112023013292A BR 112023013292 A2 BR112023013292 A2 BR 112023013292A2
Authority
BR
Brazil
Prior art keywords
substrate
core layer
matching
interconnections
layer configured
Prior art date
Application number
BR112023013292A
Other languages
English (en)
Portuguese (pt)
Inventor
Aniket Patil
Bok We Hong
Rey Villarba Buot Joan
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112023013292A2 publication Critical patent/BR112023013292A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0248—Skew reduction or using delay lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4694—Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/209—Vertical interconnections, e.g. vias
    • H10W44/212—Coaxial feed-throughs in substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/223—Differential pair signal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Combinations Of Printed Boards (AREA)
BR112023013292A 2021-01-13 2021-12-10 Substrato compreendendo interconexões em uma camada de núcleo configurada para correspondência de skew BR112023013292A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/148,257 US11955409B2 (en) 2021-01-13 2021-01-13 Substrate comprising interconnects in a core layer configured for skew matching
PCT/US2021/062859 WO2022154914A1 (en) 2021-01-13 2021-12-10 Substrate comprising interconnects in a core layer configured for skew matching

Publications (1)

Publication Number Publication Date
BR112023013292A2 true BR112023013292A2 (pt) 2023-10-31

Family

ID=79283142

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112023013292A BR112023013292A2 (pt) 2021-01-13 2021-12-10 Substrato compreendendo interconexões em uma camada de núcleo configurada para correspondência de skew

Country Status (7)

Country Link
US (1) US11955409B2 (https=)
EP (1) EP4278381A1 (https=)
JP (1) JP2024503352A (https=)
KR (1) KR20230130628A (https=)
CN (1) CN116686396A (https=)
BR (1) BR112023013292A2 (https=)
WO (1) WO2022154914A1 (https=)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001298273A (ja) * 2000-04-17 2001-10-26 Hitachi Ltd 電子部品内蔵実装基板及びそれを用いた半導体パッケージ
US7180011B1 (en) * 2006-03-17 2007-02-20 Lsi Logic Corporation Device for minimizing differential pair length mismatch and impedance discontinuities in an integrated circuit package design
US8319111B2 (en) 2006-10-04 2012-11-27 Ngk Spark Plug Co., Ltd. Wiring board having wiring laminate portion with via conductors embedded in resin insulating layers
JP2012009510A (ja) 2010-06-22 2012-01-12 Sumitomo Bakelite Co Ltd 金属微細パターン付き基材、プリント配線板、及び半導体装置、並びに、金属微細パターン付き基材及びプリント配線板の製造方法
JP2013093405A (ja) 2011-10-25 2013-05-16 Ngk Spark Plug Co Ltd 配線基板及びその製造方法
JP2014032978A (ja) * 2012-07-31 2014-02-20 Ibiden Co Ltd インダクタ部品、インダクタ部品の製造方法及び配線板
JPWO2019194200A1 (ja) * 2018-04-04 2021-04-01 太陽誘電株式会社 部品内蔵基板

Also Published As

Publication number Publication date
WO2022154914A1 (en) 2022-07-21
JP2024503352A (ja) 2024-01-25
TW202232703A (zh) 2022-08-16
CN116686396A (zh) 2023-09-01
EP4278381A1 (en) 2023-11-22
US11955409B2 (en) 2024-04-09
KR20230130628A (ko) 2023-09-12
US20220223499A1 (en) 2022-07-14

Similar Documents

Publication Publication Date Title
BR112018068923A2 (pt) formação de acessos de interconexão vertciais autoalinhados (vias) em estruturas de interconexão para circuitos integrados (ics)
CN107112244B (zh) 衬底中的垂直沟槽布线
EP4181191A3 (en) Microelectronic assemblies
MY201016A (en) Integrated Bridge for Die-to-Die Interconnects
BR112022016578A2 (pt) Pacote de semicondutores compreendendo um substrato e uma estrutura de interconexão de alta densidade acoplada ao mesmo
BR112013001256A2 (pt) Pacote microeletrônico
US9564407B2 (en) Crosstalk polarity reversal and cancellation through substrate material
TWI260056B (en) Module structure having an embedded chip
Shi et al. A 14nm FinFET transistor-level 3D partitioning design to enable high-performance and low-cost monolithic 3D IC
SG161188A1 (en) Reliable interconnect integration
MY202209A (en) Electronic device and crosstalk mitigating substrate
CN208044474U (zh) 主机板及计算机装置
WO2018043184A1 (ja) 貫通電極基板、貫通電極基板の製造方法及び実装基板
BR112023013292A2 (pt) Substrato compreendendo interconexões em uma camada de núcleo configurada para correspondência de skew
BR112023018620A2 (pt) Pacote com substrato que compreende interconexões de almofada sobre almofada
BR112023002754A2 (pt) Dispositivo, pacote e/ou substrato compreendendo antena curva
CN106865486A (zh) 电容式指纹传感器及其形成方法和电子产品
CN105609466B (zh) 金属区段作为接着垫及ic装置中的区域互连件
US12327794B2 (en) Die coupling using a substrate with a glass core
CN103987191A (zh) 一种减小ac耦合电容pad对高速串行信号传输影响的方法
BR112023013290A2 (pt) Pacote compreendendo um substrato e dispositivo de interconexão configurado para roteamento diagonal
BR112023025870A2 (pt) Pacote com um substrato compreendendo um capacitor embarcado com acoplamento em parede lateral
WO2009057444A1 (ja) 回路基板及び表示装置
EP4514088A3 (en) Internal node jumper for memory bit cells
CN108364949B (zh) 一种实现芯片互联超高带宽的方法及芯片互联结构