BR112018068923A2 - formação de acessos de interconexão vertciais autoalinhados (vias) em estruturas de interconexão para circuitos integrados (ics) - Google Patents

formação de acessos de interconexão vertciais autoalinhados (vias) em estruturas de interconexão para circuitos integrados (ics)

Info

Publication number
BR112018068923A2
BR112018068923A2 BR112018068923A BR112018068923A BR112018068923A2 BR 112018068923 A2 BR112018068923 A2 BR 112018068923A2 BR 112018068923 A BR112018068923 A BR 112018068923A BR 112018068923 A BR112018068923 A BR 112018068923A BR 112018068923 A2 BR112018068923 A2 BR 112018068923A2
Authority
BR
Brazil
Prior art keywords
self
metal line
underlying
recess
underlying metal
Prior art date
Application number
BR112018068923A
Other languages
English (en)
Inventor
Fei Yeap Choh
Junhao Xu Jeffrey
Jianhong Zhu John
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018068923A2 publication Critical patent/BR112018068923A2/pt

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

é revelada a formação de acessos de interconexão verticais autoalinhados (vias) em estruturas de interconexão para circuitos integrados (ics). para reduzir ou evitar o desalinhamento de uma via com uma linha de metal interconectada subjacente, as vias são fabricadas na estrutura de interconexão para serem autoalinhadas a uma linha de metal interconectada subjacente. nesse sentido, as linhas de metal subjacentes são formadas em uma camada dielétrica. uma reentrância é formada em uma linha de metal subjacente abaixo de uma superfície de topo de um dielétrico inter-camadas. uma camada de parada é disposta acima do dielétrico inter-camadas dentro da reentrância da linha de metal subjacente. a camada de parada permite que um túnel de via seja formado (por exemplo, causticado) abaixo dentro da reentrância da linha de metal subjacente para autoalinhar o túnel de via à linha de metal subjacente. um material condutor é, então, depositado no túnel de via que se estende na reentrância para formar a via autoalinhada interconectada à linha de metal subjacente.
BR112018068923A 2016-03-21 2017-03-17 formação de acessos de interconexão vertciais autoalinhados (vias) em estruturas de interconexão para circuitos integrados (ics) BR112018068923A2 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662310951P 2016-03-21 2016-03-21
US15/229,535 US10354912B2 (en) 2016-03-21 2016-08-05 Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs)
PCT/US2017/022868 WO2017165206A1 (en) 2016-03-21 2017-03-17 Forming self-aligned vertical interconnect accesses (vias) in interconnect structures for integrated circuits (ics)

Publications (1)

Publication Number Publication Date
BR112018068923A2 true BR112018068923A2 (pt) 2019-01-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018068923A BR112018068923A2 (pt) 2016-03-21 2017-03-17 formação de acessos de interconexão vertciais autoalinhados (vias) em estruturas de interconexão para circuitos integrados (ics)

Country Status (8)

Country Link
US (1) US10354912B2 (pt)
EP (1) EP3433877B1 (pt)
JP (1) JP2019509640A (pt)
KR (1) KR20180124045A (pt)
CN (1) CN108886018B (pt)
BR (1) BR112018068923A2 (pt)
TW (1) TW201801275A (pt)
WO (1) WO2017165206A1 (pt)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10879120B2 (en) * 2016-11-28 2020-12-29 Taiwan Semiconductor Manufacturing Self aligned via and method for fabricating the same
DE112016007377T5 (de) * 2016-12-29 2019-07-25 Intel Corporation Selbstausgerichtete durchkontaktierung
EP3499557A1 (en) * 2017-12-15 2019-06-19 Micromaterials LLC Selectively etched self-aligned via processes
SG11202009105YA (en) 2018-03-20 2020-10-29 Tokyo Electron Ltd Self-aware and correcting heterogenous platform incorporating integrated semiconductor processing modules and method for using same
US10790191B2 (en) 2018-05-08 2020-09-29 Micromaterials Llc Selective removal process to create high aspect ratio fully self-aligned via
US10622301B2 (en) 2018-08-17 2020-04-14 International Business Machines Corporation Method of forming a straight via profile with precise critical dimension control
US10727124B2 (en) 2018-10-29 2020-07-28 International Business Machines Corporation Structure and method for forming fully-aligned trench with an up-via integration scheme
US11502001B2 (en) * 2018-10-31 2022-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with self-aligned vias
KR20200122189A (ko) * 2019-04-17 2020-10-27 삼성전자주식회사 집적회로 소자의 제조 방법
SG10202003450RA (en) * 2019-05-02 2020-12-30 Asm Tech Singapore Pte Ltd Method for measuring the heights of wire interconnections
US11232986B2 (en) 2019-10-11 2022-01-25 Samsung Electronics Co., Ltd. Integrated circuit devices including enlarged via and fully aligned metal wire and methods of forming the same
US11069610B2 (en) * 2019-10-15 2021-07-20 Micron Technology, Inc. Methods for forming microelectronic devices with self-aligned interconnects, and related devices and systems
US11244860B2 (en) 2019-10-22 2022-02-08 International Business Machines Corporation Double patterning interconnect integration scheme with SAV
US11264276B2 (en) 2019-10-22 2022-03-01 International Business Machines Corporation Interconnect integration scheme with fully self-aligned vias
US11152261B2 (en) 2019-10-26 2021-10-19 International Business Machines Corporation Self-aligned top via formation at line ends
US11217481B2 (en) * 2019-11-08 2022-01-04 International Business Machines Corporation Fully aligned top vias
CN112838048A (zh) 2019-11-22 2021-05-25 联华电子股份有限公司 互连结构以及其制作方法
EP3836198B1 (en) 2019-12-12 2022-08-24 Imec VZW A method for forming a via hole self-aligned with a metal block on a substrate
US11257677B2 (en) 2020-01-24 2022-02-22 Applied Materials, Inc. Methods and devices for subtractive self-alignment
US11488864B2 (en) 2020-10-02 2022-11-01 Samsung Electronics Co., Ltd. Self-aligned supervia and metal direct etching process to manufacture self-aligned supervia
US11916013B2 (en) 2021-09-02 2024-02-27 International Business Machines Corporation Via interconnects including super vias
US11978668B2 (en) 2021-09-09 2024-05-07 Samsung Electronics Co., Ltd. Integrated circuit devices including a via and methods of forming the same

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6194316B1 (en) * 1998-08-10 2001-02-27 Vacuum Metallurgical Co., Ltd. Method for forming CU-thin film
CA2393391C (en) * 2000-01-12 2009-10-27 Martin J. T. Reaney Method for commercial preparation of preferred isomeric forms of ester free conjugated fatty acids with solvent systems containing polyether alcohol solvents
FR2814449B1 (fr) * 2000-09-25 2003-02-07 Christian Salesse Dispositif de deplacement d'une charge
US7252875B2 (en) * 2002-12-16 2007-08-07 International Business Machines Corporation Diffusion barrier with low dielectric constant and semiconductor device containing same
US6838300B2 (en) * 2003-02-04 2005-01-04 Texas Instruments Incorporated Chemical treatment of low-k dielectric films
US20060175708A1 (en) * 2005-02-10 2006-08-10 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
US7741224B2 (en) * 2007-07-11 2010-06-22 Texas Instruments Incorporated Plasma treatment and repair processes for reducing sidewall damage in low-k dielectrics
US8466068B2 (en) * 2007-12-31 2013-06-18 Sandisk 3D Llc Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography
US8013333B2 (en) * 2008-11-07 2011-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor test pad structures
DE102010027875A1 (de) * 2010-04-16 2011-10-20 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement und Verfahren zum Herstellen eines optoelektronischen Bauelements
FR2969375A1 (fr) 2010-12-17 2012-06-22 St Microelectronics Crolles 2 Structure d'interconnexion pour circuit intégré
US8664113B2 (en) 2011-04-28 2014-03-04 GlobalFoundries, Inc. Multilayer interconnect structure and method for integrated circuits
US20130013438A1 (en) * 2011-07-05 2013-01-10 Li-Hui Chen Grouping Method for Group-buying Based on Wireless Communication Protocol
KR20130060065A (ko) * 2011-11-29 2013-06-07 에스케이하이닉스 주식회사 비휘발성 메모리 장치 및 이의 제조 방법
WO2013101204A1 (en) 2011-12-30 2013-07-04 Intel Corporation Self-enclosed asymmetric interconnect structures
US8669661B2 (en) 2012-02-10 2014-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. Metal line and via formation using hard masks
US8759807B2 (en) * 2012-03-22 2014-06-24 Micron Technology, Inc. Memory cells
US9054109B2 (en) 2012-05-29 2015-06-09 International Business Machines Corporation Corrosion/etching protection in integration circuit fabrications
US8803321B2 (en) * 2012-06-07 2014-08-12 International Business Machines Corporation Dual damascene dual alignment interconnect scheme
US9152870B2 (en) * 2013-03-15 2015-10-06 Sri International Computer vision as a service
US9312204B2 (en) 2013-09-27 2016-04-12 Intel Corporation Methods of forming parallel wires of different metal materials through double patterning and fill techniques
US9583429B2 (en) 2013-11-14 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of forming same
US9324650B2 (en) * 2014-08-15 2016-04-26 International Business Machines Corporation Interconnect structures with fully aligned vias

Also Published As

Publication number Publication date
EP3433877B1 (en) 2022-07-06
US20170271202A1 (en) 2017-09-21
JP2019509640A (ja) 2019-04-04
CN108886018B (zh) 2023-04-11
CN108886018A (zh) 2018-11-23
EP3433877A1 (en) 2019-01-30
KR20180124045A (ko) 2018-11-20
TW201801275A (zh) 2018-01-01
WO2017165206A1 (en) 2017-09-28
US10354912B2 (en) 2019-07-16

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