BR112022019588A2 - Pacote compreendendo um substrato com interconexão de roteamento sobre camada resistente à solda - Google Patents

Pacote compreendendo um substrato com interconexão de roteamento sobre camada resistente à solda

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Publication number
BR112022019588A2
BR112022019588A2 BR112022019588A BR112022019588A BR112022019588A2 BR 112022019588 A2 BR112022019588 A2 BR 112022019588A2 BR 112022019588 A BR112022019588 A BR 112022019588A BR 112022019588 A BR112022019588 A BR 112022019588A BR 112022019588 A2 BR112022019588 A2 BR 112022019588A2
Authority
BR
Brazil
Prior art keywords
substrate
package
dielectric layer
layer
routing
Prior art date
Application number
BR112022019588A
Other languages
English (en)
Inventor
Patil Aniket
Bok We Hong
Kang Kuiwon
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112022019588A2 publication Critical patent/BR112022019588A2/pt

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    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)

Abstract

PACOTE COMPREENDENDO UM SUBSTRATO COM INTERCONEXÃO DE ROTEAMENTO SOBRE CAMADA RESISTENTE À SOLDA. Um pacote compreendendo um substrato e um dispositivo integrado acoplado ao substrato. O substrato inclui (i) pelo menos uma camada dielétrica interna, (ii) uma pluralidade de interconexões localizadas na pelo menos uma camada dielétrica interna, onde a pluralidade de interconexões inclui uma almofada (pad) localizada em uma camada de metal inferior do substrato, (iii) uma camada dielétrica externa localizada sobre a pelo menos uma camada dielétrica, (iv) pelo menos uma interconexão de roteamento acoplada à pluralidade de interconexões, onde a pelo menos uma interconexão de roteamento está localizada sobre a camada dielétrica externa, onde a pelo menos uma interconexão de roteamento a interconexão está localizada abaixo da camada de metal inferior do substrato e (v) uma camada dielétrica de cobertura localizada sobre a camada dielétrica externa e a pelo menos uma interconexão de roteamento. O pacote inclui uma interconexão de solda acoplada à almofada localizada na camada metálica inferior do substrato.
BR112022019588A 2020-04-06 2021-04-05 Pacote compreendendo um substrato com interconexão de roteamento sobre camada resistente à solda BR112022019588A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/840,752 US11444019B2 (en) 2020-04-06 2020-04-06 Package comprising a substrate with interconnect routing over solder resist layer and an integrated device coupled to the substrate and method for manufacturing the package
PCT/US2021/025822 WO2021207101A2 (en) 2020-04-06 2021-04-05 Package comprising a substrate with interconnect routing over solder resist layer

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BR112022019588A2 true BR112022019588A2 (pt) 2022-11-16

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US (1) US11444019B2 (pt)
EP (1) EP4133521B1 (pt)
KR (1) KR20220165246A (pt)
CN (1) CN115362550A (pt)
BR (1) BR112022019588A2 (pt)
TW (1) TW202203407A (pt)
WO (1) WO2021207101A2 (pt)

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JP2022019309A (ja) * 2020-07-17 2022-01-27 ローム株式会社 半導体装置
US11749611B2 (en) * 2021-02-01 2023-09-05 Qualcomm Incorporated Package with a substrate comprising periphery interconnects
US11682607B2 (en) * 2021-02-01 2023-06-20 Qualcomm Incorporated Package having a substrate comprising surface interconnects aligned with a surface of the substrate

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US8610134B2 (en) 2006-06-29 2013-12-17 Cree, Inc. LED package with flexible polyimide circuit and method of manufacturing LED package
US8633588B2 (en) 2011-12-21 2014-01-21 Mediatek Inc. Semiconductor package
US9642259B2 (en) * 2013-10-30 2017-05-02 Qualcomm Incorporated Embedded bridge structure in a substrate
US9721922B2 (en) 2013-12-23 2017-08-01 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming fine pitch RDL over semiconductor die in fan-out package
KR102434823B1 (ko) 2014-03-10 2022-08-19 데카 테크놀로지 유에스에이 인코포레이티드 두꺼운 재배선 층을 포함하는 반도체 디바이스 및 방법
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MY202342A (en) * 2017-06-08 2024-04-24 Intel Corp Over-molded ic package with in-mold capacitor
US11728265B2 (en) * 2018-09-12 2023-08-15 Intel Corporation Selective deposition of embedded thin-film resistors for semiconductor packaging
US11164814B2 (en) * 2019-03-14 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same

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Publication number Publication date
US20210313266A1 (en) 2021-10-07
CN115362550A (zh) 2022-11-18
US11444019B2 (en) 2022-09-13
TW202203407A (zh) 2022-01-16
EP4133521B1 (en) 2024-05-08
EP4133521A2 (en) 2023-02-15
WO2021207101A3 (en) 2021-11-18
KR20220165246A (ko) 2022-12-14
WO2021207101A2 (en) 2021-10-14

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