BR112022011437A2 - Método de gerar retardo ou frequência de tempo preciso e estável a pvt utilizando circuitos cmos - Google Patents

Método de gerar retardo ou frequência de tempo preciso e estável a pvt utilizando circuitos cmos

Info

Publication number
BR112022011437A2
BR112022011437A2 BR112022011437A BR112022011437A BR112022011437A2 BR 112022011437 A2 BR112022011437 A2 BR 112022011437A2 BR 112022011437 A BR112022011437 A BR 112022011437A BR 112022011437 A BR112022011437 A BR 112022011437A BR 112022011437 A2 BR112022011437 A2 BR 112022011437A2
Authority
BR
Brazil
Prior art keywords
pvt
frequency
pair
stable time
cmos circuits
Prior art date
Application number
BR112022011437A
Other languages
English (en)
Inventor
Wu Zhengzheng
Zhang Xu
Huang Xuhao
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112022011437A2 publication Critical patent/BR112022011437A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H03K2005/00045—Dc voltage control of a capacitor or of the coupling of a capacitor as a load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H03K3/0322—Ring oscillators with differential cells

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)

Abstract

MÉTODO DE GERAR RETARDO OU FREQUÊNCIA DE TEMPO PRECISO E ESTÁVEL A PVT UTILIZANDO CIRCUITOS CMOS. Um método de geração de retardo ou frequência de tempo precisa e estável PVT utilizando circuitos CMOS é revelado. Em algumas implementações, o método inclui proporcionar uma tensão de referência utilizando um módulo resistivo em um terminal de entrada positivo de um amplificador operacional, portas de acoplamento de um par de transistores de semicondutor de óxido metálico tipo p (pMOS) e um capacitor de compensação para um terminal de saída do amplificador operacional para gerar um primeiro sinal de polarização e acoplar um par de transistores semicondutores de óxido metálico tipo n (nMOS) a um terminal negativo do amplificador operacional para gerar um segundo sinal de polarização no terminal negativo, em que o par de transistores nMOS é substancialmente o mesmo que um par de transistores nMOS no circuito de retardo CMOS.
BR112022011437A 2019-12-20 2020-10-28 Método de gerar retardo ou frequência de tempo preciso e estável a pvt utilizando circuitos cmos BR112022011437A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/722,572 US10812056B1 (en) 2019-12-20 2019-12-20 Method of generating precise and PVT-stable time delay or frequency using CMOS circuits
PCT/US2020/057693 WO2021126373A1 (en) 2019-12-20 2020-10-28 Method of generating precise and pvt-stable time delay or frequency using cmos circuits

Publications (1)

Publication Number Publication Date
BR112022011437A2 true BR112022011437A2 (pt) 2022-08-30

Family

ID=72838554

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112022011437A BR112022011437A2 (pt) 2019-12-20 2020-10-28 Método de gerar retardo ou frequência de tempo preciso e estável a pvt utilizando circuitos cmos

Country Status (8)

Country Link
US (2) US10812056B1 (pt)
EP (1) EP4078811A1 (pt)
JP (1) JP2022552915A (pt)
KR (1) KR102463655B1 (pt)
CN (1) CN114830534A (pt)
BR (1) BR112022011437A2 (pt)
TW (1) TW202133558A (pt)
WO (1) WO2021126373A1 (pt)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11239806B2 (en) * 2019-03-25 2022-02-01 Northeastern University High stability gain structure and filter realization with less than 50 ppm/° c. temperature variation with ultra-low power consumption using switched-capacitor and sub-threshold biasing
US10812056B1 (en) * 2019-12-20 2020-10-20 Qualcomm Incorporated Method of generating precise and PVT-stable time delay or frequency using CMOS circuits
WO2022106960A1 (en) * 2020-11-23 2022-05-27 Silanna Asia Pte Ltd Noise-tolerant delay circuit
CN112736076B (zh) * 2020-12-29 2024-05-10 中国科学院上海微系统与信息技术研究所 自加热效应参数的提取装置以及提取方法
KR20220153964A (ko) * 2021-05-12 2022-11-21 삼성전자주식회사 전원 전압 변화를 보상하는 인터페이스 회로 및 이의 동작 방법

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6043718A (en) * 1998-08-31 2000-03-28 Analog Devices, Inc. Temperature, supply and process-insensitive signal-controlled oscillators
JP4796927B2 (ja) * 2005-11-28 2011-10-19 株式会社豊田中央研究所 クロック信号出力回路
US7498885B2 (en) * 2006-11-03 2009-03-03 Taiwan Semiconductor Manufacturing Co., Ltd. Voltage controlled oscillator with gain compensation
US7777581B2 (en) * 2007-10-19 2010-08-17 Diablo Technologies Inc. Voltage Controlled Oscillator (VCO) with a wide tuning range and substantially constant voltage swing over the tuning range
US7586380B1 (en) * 2008-03-12 2009-09-08 Kawasaki Microelectronics, Inc. Bias circuit to stabilize oscillation in ring oscillator, oscillator, and method to stabilize oscillation in ring oscillator
US7834709B2 (en) * 2008-10-03 2010-11-16 Plx Technology, Inc. Circuit for voltage controlled oscillator
JP5215115B2 (ja) * 2008-10-20 2013-06-19 旭化成エレクトロニクス株式会社 差動増幅回路及びこれを用いたリングオシレータ回路
US7924102B2 (en) * 2009-02-23 2011-04-12 Qualcomm Incorporated Symmetric load delay cell oscillator
US7948330B2 (en) * 2009-03-19 2011-05-24 Qualcomm Incorporated Current controlled oscillator with regulated symmetric loads
US8604884B2 (en) * 2011-06-30 2013-12-10 Silicon Laboratories Inc. VCO insensitive to power supply ripple
TWI505640B (zh) 2011-11-04 2015-10-21 Sitronix Technology Corp Oscillating device
US8970311B2 (en) * 2012-02-27 2015-03-03 Mohammad Ardehali Voltage-controlled oscillator with amplitude and frequency independent of process variations and temperature
US8742815B2 (en) * 2012-06-20 2014-06-03 Qualcomm Incorporated Temperature-independent oscillators and delay elements
US10812056B1 (en) * 2019-12-20 2020-10-20 Qualcomm Incorporated Method of generating precise and PVT-stable time delay or frequency using CMOS circuits

Also Published As

Publication number Publication date
TW202133558A (zh) 2021-09-01
WO2021126373A1 (en) 2021-06-24
KR20220084179A (ko) 2022-06-21
JP2022552915A (ja) 2022-12-20
EP4078811A1 (en) 2022-10-26
US11196410B2 (en) 2021-12-07
CN114830534A (zh) 2022-07-29
KR102463655B1 (ko) 2022-11-03
US10812056B1 (en) 2020-10-20
US20210194474A1 (en) 2021-06-24

Similar Documents

Publication Publication Date Title
BR112022011437A2 (pt) Método de gerar retardo ou frequência de tempo preciso e estável a pvt utilizando circuitos cmos
US9438175B2 (en) Cascode amplifier
US9350304B2 (en) Quiescent current equalization method, output stage circuit, class AB amplifier and electronic device
US10539470B2 (en) Sub-threshold-based semiconductor temperature sensor
KR102407546B1 (ko) 스큐 검출 회로 및 이를 이용한 입력 회로
JP2009098802A (ja) 基準電圧発生回路
JP2011155488A (ja) 差動入力段回路、差動入力段回路を備えた演算増幅器及び電圧レギュレータ回路
Haga et al. Bulk-driven flipped voltage follower
KR950010335A (ko) 저동작전압에서 작동이 가능하고, 고출력 임피던스를 갖는 케스코드 회로
DE602004006734D1 (de) Schmitt-trigger-schaltung in soi-technik
US7786800B2 (en) Class AB amplifier
US10824181B2 (en) Reference voltage circuit and semiconductor device
CN109756211B (zh) 一种窄脉冲延时电路
US9543905B2 (en) Amplifier circuit
TWI614992B (zh) 高壓電路
TWI644195B (zh) 緩衝級和控制電路
US20130002355A1 (en) Differential amplifier and comparator
US20100156389A1 (en) Reducing the effect of bulk leakage currents
JP6672067B2 (ja) 安定化電源回路
TWM576366U (zh) 具輔助電路之位準轉換電路
JP6320047B2 (ja) 定電圧源回路
Veldandi et al. A 1-V high-gain two-stage self-cascode operational transconductance amplifier
TWM408885U (en) signal generating circuit
US10715090B2 (en) Bias circuit with a replica circuit for an amplifier circuit and a generation circuit supplying bias voltage to the replica and amplifier circuits and optical receiver
US11575367B1 (en) Flip-flop circuit and asynchronous receiving circuit