BR112018069830A2 - esquema de ajuste de linha de palavra - Google Patents

esquema de ajuste de linha de palavra

Info

Publication number
BR112018069830A2
BR112018069830A2 BR112018069830A BR112018069830A BR112018069830A2 BR 112018069830 A2 BR112018069830 A2 BR 112018069830A2 BR 112018069830 A BR112018069830 A BR 112018069830A BR 112018069830 A BR112018069830 A BR 112018069830A BR 112018069830 A2 BR112018069830 A2 BR 112018069830A2
Authority
BR
Brazil
Prior art keywords
word line
memory
memory cell
transistor
line fit
Prior art date
Application number
BR112018069830A
Other languages
English (en)
Inventor
Saru Rahul
Kumar Gupta Sharad
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018069830A2 publication Critical patent/BR112018069830A2/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits

Abstract

a presente invenção refere-se a uma memória e um método para operar uma memória. a memória inclui uma célula de memória que tem um transistor e um driver de linha de palavra que fornece uma linha de palavra acoplada à célula de memória. o driver de linha de palavra ajusta um nível de tensão da linha de palavra para compensar um parâmetro do transistor. o método inclui verificar uma tensão de linha de palavra para acessar uma célula de memória que tem um transistor e ajustar a tensão de linha de palavra para compensar um parâmetro do transistor. outra memória é fornecida. a memória inclui uma célula de memória e um driver de linha de palavra que fornece uma linha de palavra acoplada à célula de memória. o driver de linha de palavra ajusta um nível de tensão da linha de palavra com base em um feedback da linha de palavra.
BR112018069830A 2016-03-30 2017-02-24 esquema de ajuste de linha de palavra BR112018069830A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/085,942 US9928898B2 (en) 2016-03-30 2016-03-30 Wordline adjustment scheme
PCT/US2017/019488 WO2017172150A1 (en) 2016-03-30 2017-02-24 Wordline adjustment scheme

Publications (1)

Publication Number Publication Date
BR112018069830A2 true BR112018069830A2 (pt) 2019-01-29

Family

ID=58231789

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018069830A BR112018069830A2 (pt) 2016-03-30 2017-02-24 esquema de ajuste de linha de palavra

Country Status (7)

Country Link
US (1) US9928898B2 (pt)
EP (1) EP3437098B1 (pt)
JP (1) JP6545915B2 (pt)
KR (1) KR102054920B1 (pt)
CN (1) CN108885890B (pt)
BR (1) BR112018069830A2 (pt)
WO (1) WO2017172150A1 (pt)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10811088B2 (en) * 2019-03-12 2020-10-20 Qualcomm Incorporated Access assist with wordline adjustment with tracking cell
US20230008275A1 (en) * 2021-07-09 2023-01-12 Stmicroelectronics International N.V. Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)
US20230260572A1 (en) * 2022-02-15 2023-08-17 Taiwan Semiconductor Manufacturing Company Ltd. Electronic circuits, memory devices, and methods for operating an electronic circuit
US11842769B2 (en) * 2022-04-14 2023-12-12 Macronix International Co., Ltd. Memory circuit with leakage current blocking mechanism and memory device having the memory circuit

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US5410508A (en) * 1993-05-14 1995-04-25 Micron Semiconductor, Inc. Pumped wordlines
JP3239867B2 (ja) 1998-12-17 2001-12-17 日本電気株式会社 半導体装置
JP4408610B2 (ja) * 2002-08-09 2010-02-03 株式会社ルネサステクノロジ スタティック型半導体記憶装置
JP2007523585A (ja) 2004-02-17 2007-08-16 アギア システムズ インコーポレーテッド 多用途のインテリジェントな電源コントローラ
US7532501B2 (en) * 2005-06-02 2009-05-12 International Business Machines Corporation Semiconductor device including back-gated transistors and method of fabricating the device
JP5100035B2 (ja) 2005-08-02 2012-12-19 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP5158624B2 (ja) * 2006-08-10 2013-03-06 ルネサスエレクトロニクス株式会社 半導体記憶装置
US8213257B2 (en) * 2010-08-09 2012-07-03 Faraday Technology Corp. Variation-tolerant word-line under-drive scheme for random access memory
US8228713B2 (en) 2010-09-28 2012-07-24 International Business Machines Corporation SRAM having wordline up-level voltage adjustable to assist bitcell stability and design structure for same
US8493812B2 (en) * 2010-10-28 2013-07-23 International Business Machines Corporation Boost circuit for generating an adjustable boost voltage
US9105315B2 (en) 2012-07-23 2015-08-11 Arm Limited Controlling the voltage level on the word line to maintain performance and reduce access disturbs
JP2014086112A (ja) 2012-10-24 2014-05-12 Fujitsu Semiconductor Ltd 半導体記憶装置
KR102083496B1 (ko) 2012-11-21 2020-03-02 삼성전자 주식회사 리드 동작 시 온도 보상된 워드 라인 전압을 인가하는 반도체 메모리 장치 및 그 방법
US9202579B2 (en) 2013-03-14 2015-12-01 Sandisk Technologies Inc. Compensation for temperature dependence of bit line resistance
US9257199B2 (en) 2013-07-24 2016-02-09 Advanced Micro Devices, Inc. Canary circuit with passgate transistor variation
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Also Published As

Publication number Publication date
CN108885890A (zh) 2018-11-23
JP2019510333A (ja) 2019-04-11
CN108885890B (zh) 2020-01-03
EP3437098A1 (en) 2019-02-06
JP6545915B2 (ja) 2019-07-17
WO2017172150A1 (en) 2017-10-05
US20170287551A1 (en) 2017-10-05
EP3437098B1 (en) 2019-07-24
KR20180113615A (ko) 2018-10-16
KR102054920B1 (ko) 2019-12-11
US9928898B2 (en) 2018-03-27

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Legal Events

Date Code Title Description
B350 Update of information on the portal [chapter 15.35 patent gazette]
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 6A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: EM VIRTUDE DO ARQUIVAMENTO PUBLICADO NA RPI 2711 DE 20-12-2022 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDO O ARQUIVAMENTO DO PEDIDO DE PATENTE, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.