BR112018001783B8 - Estrutura de pacote sobre pacote (pop) incluindo várias pastilhas - Google Patents

Estrutura de pacote sobre pacote (pop) incluindo várias pastilhas

Info

Publication number
BR112018001783B8
BR112018001783B8 BR112018001783A BR112018001783A BR112018001783B8 BR 112018001783 B8 BR112018001783 B8 BR 112018001783B8 BR 112018001783 A BR112018001783 A BR 112018001783A BR 112018001783 A BR112018001783 A BR 112018001783A BR 112018001783 B8 BR112018001783 B8 BR 112018001783B8
Authority
BR
Brazil
Prior art keywords
matrix
pop
package
structure including
pid
Prior art date
Application number
BR112018001783A
Other languages
English (en)
Portuguese (pt)
Other versions
BR112018001783B1 (pt
BR112018001783A2 (pt
Inventor
Bok We Hong
Sik Lee Jae
Wook Kim Dong
Gu Shiqun
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018001783A2 publication Critical patent/BR112018001783A2/pt
Publication of BR112018001783B1 publication Critical patent/BR112018001783B1/pt
Publication of BR112018001783B8 publication Critical patent/BR112018001783B8/pt

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Medical Preparation Storing Or Oral Administration Devices (AREA)
  • Packages (AREA)
  • Hybrid Cells (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Die Bonding (AREA)
  • Packaging Frangible Articles (AREA)
  • Optical Measuring Cells (AREA)
  • Measurement Of Radiation (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
BR112018001783A 2015-07-29 2016-07-28 Estrutura de pacote sobre pacote (pop) incluindo várias pastilhas BR112018001783B8 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/812,476 US9401350B1 (en) 2015-07-29 2015-07-29 Package-on-package (POP) structure including multiple dies
US14/812,476 2015-07-29
PCT/US2016/044487 WO2017019866A1 (en) 2015-07-29 2016-07-28 Package-on-package (pop) structure including multiple dies

Publications (3)

Publication Number Publication Date
BR112018001783A2 BR112018001783A2 (pt) 2018-09-11
BR112018001783B1 BR112018001783B1 (pt) 2023-01-31
BR112018001783B8 true BR112018001783B8 (pt) 2023-02-14

Family

ID=56411293

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018001783A BR112018001783B8 (pt) 2015-07-29 2016-07-28 Estrutura de pacote sobre pacote (pop) incluindo várias pastilhas

Country Status (7)

Country Link
US (1) US9401350B1 (https=)
EP (2) EP3329512A1 (https=)
JP (1) JP6914245B2 (https=)
KR (1) KR102546223B1 (https=)
CN (1) CN107851588B (https=)
BR (1) BR112018001783B8 (https=)
WO (1) WO2017019866A1 (https=)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3465751B1 (en) * 2016-06-03 2021-08-18 Intel Corporation Wireless module with antenna package and cap package
US9837341B1 (en) * 2016-09-15 2017-12-05 Intel Corporation Tin-zinc microbump structures
WO2018182610A1 (en) * 2017-03-30 2018-10-04 Intel Corporation Package architecture utilizing photoimageable dielectric (pid) for reduced bump pitch
EP3602642A4 (en) * 2017-03-31 2020-12-23 3M Innovative Properties Company ELECTRONIC DEVICES INCLUDING SOLID SEMICONDUCTOR CHIPS
WO2020020825A1 (en) 2018-07-23 2020-01-30 Borealis Ag Multilayer polypropylene film
US10665572B2 (en) * 2018-08-15 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US20200083154A1 (en) 2018-09-10 2020-03-12 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component Carrier With a Photoimageable Dielectric Layer and a Structured Conductive Layer Being Used as a Mask for Selectively Exposing the Photoimageable Dielectric Layer With Electromagnetic Radiation
WO2020103147A1 (zh) 2018-11-23 2020-05-28 北京比特大陆科技有限公司 芯片散热结构、芯片结构、电路板和超算设备
EP3723459A1 (en) 2019-04-10 2020-10-14 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with high passive intermodulation (pim) performance
WO2020245251A2 (en) 2019-06-05 2020-12-10 Borealis Ag Multilayer polyproplyene film
KR102764370B1 (ko) 2019-12-26 2025-02-07 삼성전자주식회사 반도체 패키지
CN112867243A (zh) * 2021-01-06 2021-05-28 英韧科技(上海)有限公司 多层电路板
US20230134317A1 (en) * 2021-11-04 2023-05-04 Innolux Corporation Electrical connection structure and electronic device including the same
US20240222142A1 (en) * 2022-12-28 2024-07-04 Applied Materials, Inc. Efficient autocatalytic metallization of polymeric surfaces

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5798909A (en) 1995-02-15 1998-08-25 International Business Machines Corporation Single-tiered organic chip carriers for wire bond-type chips
US6437433B1 (en) 2000-03-24 2002-08-20 Andrew C. Ross CSP stacking technology using rigid/flex construction
US6404043B1 (en) 2000-06-21 2002-06-11 Dense-Pac Microsystems, Inc. Panel stacking of BGA devices to form three-dimensional modules
US7122904B2 (en) * 2002-04-25 2006-10-17 Macronix International Co., Ltd. Semiconductor packaging device and manufacture thereof
US7388294B2 (en) 2003-01-27 2008-06-17 Micron Technology, Inc. Semiconductor components having stacked dice
US20090008792A1 (en) * 2004-11-19 2009-01-08 Industrial Technology Research Institute Three-dimensional chip-stack package and active component on a substrate
US20080157316A1 (en) * 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Multi-chips package and method of forming the same
US20110024890A1 (en) * 2007-06-29 2011-02-03 Stats Chippac, Ltd. Stackable Package By Using Internal Stacking Modules
TWI338941B (en) * 2007-08-22 2011-03-11 Unimicron Technology Corp Semiconductor package structure
JP5310103B2 (ja) * 2009-03-03 2013-10-09 日本電気株式会社 半導体装置及びその製造方法
WO2010101163A1 (ja) * 2009-03-04 2010-09-10 日本電気株式会社 機能素子内蔵基板及びそれを用いた電子デバイス
US8558374B2 (en) 2011-02-08 2013-10-15 Endicott Interconnect Technologies, Inc. Electronic package with thermal interposer and method of making same
US8883561B2 (en) * 2011-04-30 2014-11-11 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP
US20130186676A1 (en) * 2012-01-20 2013-07-25 Futurewei Technologies, Inc. Methods and Apparatus for a Substrate Core Layer
US9881894B2 (en) * 2012-03-08 2018-01-30 STATS ChipPAC Pte. Ltd. Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration
CN202871783U (zh) * 2012-08-31 2013-04-10 江阴长电先进封装有限公司 一种芯片嵌入式堆叠圆片级封装结构
US20140246781A1 (en) * 2013-03-04 2014-09-04 Kabushiki Kaisha Toshiba Semiconductor device, method of forming a packaged chip device and chip package
US9455218B2 (en) * 2013-03-28 2016-09-27 Intel Corporation Embedded die-down package-on-package device
KR102065008B1 (ko) * 2013-09-27 2020-01-10 삼성전자주식회사 적층형 반도체 패키지
US20150255411A1 (en) * 2014-03-05 2015-09-10 Omkar G. Karhade Die-to-die bonding and associated package configurations

Also Published As

Publication number Publication date
CN107851588B (zh) 2020-10-16
CN107851588A (zh) 2018-03-27
EP4439634A3 (en) 2025-01-15
WO2017019866A1 (en) 2017-02-02
EP3329512A1 (en) 2018-06-06
BR112018001783B1 (pt) 2023-01-31
JP6914245B2 (ja) 2021-08-04
CA2990470A1 (en) 2017-02-02
BR112018001783A2 (pt) 2018-09-11
JP2018523919A (ja) 2018-08-23
US9401350B1 (en) 2016-07-26
KR20180035806A (ko) 2018-04-06
KR102546223B1 (ko) 2023-06-20
EP4439634A2 (en) 2024-10-02

Similar Documents

Publication Publication Date Title
BR112018001783B8 (pt) Estrutura de pacote sobre pacote (pop) incluindo várias pastilhas
BR112016025167A2 (pt) elemento de conexão elétrica para o contato de uma estrutura eletricamente condutora sobre um substrato
WO2018056694A3 (ko) 로직 반도체 소자
BR112017008727A2 (pt) estrutura de pacote de saída em leque de alta densidade
BR112018012787A2 (pt) dielétrico de dupla camada em dispositivo de memória
BR112017008729A2 (pt) estrutura de percurso para otimizar a porosidade do sinal
BR112019006998A2 (pt) interconexão
AR061279A1 (es) Cable multipolar y procedimiento para fabricarlo
AR090504A1 (es) Cable de comunicacion de datos y separador
BR112016011552A2 (pt) Redes de partições hierárquicas e paralelas
WO2015200307A3 (en) Integrated micro-electromechanical switches and a related method thereof
MX2020010331A (es) Dispositivo de pantalla y sustrato de matriz.
CL2019001555A1 (es) Preparación farmacéutica y método para su fabricación.
PE20210601A1 (es) Componente con elementos funcionales electricos para la produccion de una hoja laminada
CL2016001849A1 (es) Un disipador que comprende una base de soporte que se fija al suelo y soporta una base de contacto que se asocia con una estructura de soporte, medios de interconexión, medios de control y al menos un cuerpo de disipación tipo barra teniendo un comportamiento del tipo disipador
WO2015116051A3 (en) Thermal inkjet printhead
MX2016011948A (es) Disipador de calor.
ES2487590B1 (es) Micro-generador termoeléctrico basado en contactos eléctricos pasantes
WO2016096373A3 (de) Komponente, optisches system und lithographieanlage
MX2017003109A (es) Dispositivos dielectricos de ruta termica, y sistemas y metodos que usan los mismos.
EP3836185C0 (fr) Appareil électrique à haute tension comprenant un dispositif anti-explosion
CL2018001153A1 (es) Disipador de calor para luminarias led.
BR132015006278F1 (pt) comutador rotativo com travamento da comutação
PE20180008Z (es) Ordenador de filas publicitario
TH1701006997A (th) สวิตช์แพร่สัญญาณเฉพาะกลุ่มพื้นที่ว่างที่มีลำแสงแบบวงรี

Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 28/07/2016, OBSERVADAS AS CONDICOES LEGAIS

B16C Correction of notification of the grant [chapter 16.3 patent gazette]

Free format text: REFERENTE A RPI 2717 DE 31/01/2023, QUANTO AO ITEM (54) TITULO.