BR112016028583A2 - camada de contato de óxido de alumínio para canais condutores para um dispositivo de circuito tridimensional - Google Patents

camada de contato de óxido de alumínio para canais condutores para um dispositivo de circuito tridimensional

Info

Publication number
BR112016028583A2
BR112016028583A2 BR112016028583A BR112016028583A BR112016028583A2 BR 112016028583 A2 BR112016028583 A2 BR 112016028583A2 BR 112016028583 A BR112016028583 A BR 112016028583A BR 112016028583 A BR112016028583 A BR 112016028583A BR 112016028583 A2 BR112016028583 A2 BR 112016028583A2
Authority
BR
Brazil
Prior art keywords
layer
stack
source
poly
aluminum oxide
Prior art date
Application number
BR112016028583A
Other languages
English (en)
Other versions
BR112016028583B1 (pt
Inventor
Simsek-Ege Fatma
Haller Gordon
Zhu Hongbin
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR112016028583A2 publication Critical patent/BR112016028583A2/pt
Publication of BR112016028583B1 publication Critical patent/BR112016028583B1/pt

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

trata-se de uma pilha de múltiplos níveis de células de memória que tem uma camada de óxido de alumínio (alox) como uma camada de hik nobre para fornecer seletividade de interrupção de ataque químico. cada nível da pilha inclui um dispositivo de célula de memória. o circuito inclui uma camada policristalina de seleção de porta de fonte (poli-sgs) adjacente à pilha de múltiplos níveis de células de memória, em que a camada poli-sgs serve para fornecer um sinal de seleção de porta para as células de memória da pilha de múltiplos níveis. o circuito também inclui uma camada de fonte condutora para fornecer um condutor de fonte para um canal para os níveis da pilha. a camada de alox é disposta entre a camada de fonte e a camada poli-sgs e fornece tanto seletividade de ataque químico seco quanto seletividade de ataque químico molhado para criar um canal para acoplar eletricamente as células de memória à camada de fonte.
BR112016028583-2A 2014-07-11 2015-06-26 Dispositivo de circuito com uma camada interrupção de ataque químico, e método para criar um circuito empilhado com uma camada de interrupção de ataque químico BR112016028583B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/329,644 US9595531B2 (en) 2014-07-11 2014-07-11 Aluminum oxide landing layer for conductive channels for a three dimensional circuit device
US14/329,644 2014-07-11
PCT/US2015/037999 WO2016007315A1 (en) 2014-07-11 2015-06-26 Aluminum oxide landing layer for conductive channels for a three dimensional circuit device

Publications (2)

Publication Number Publication Date
BR112016028583A2 true BR112016028583A2 (pt) 2017-08-22
BR112016028583B1 BR112016028583B1 (pt) 2022-09-20

Family

ID=55064693

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112016028583-2A BR112016028583B1 (pt) 2014-07-11 2015-06-26 Dispositivo de circuito com uma camada interrupção de ataque químico, e método para criar um circuito empilhado com uma camada de interrupção de ataque químico

Country Status (10)

Country Link
US (2) US9595531B2 (pt)
EP (1) EP3172766A4 (pt)
JP (1) JP6442735B2 (pt)
KR (1) KR102219033B1 (pt)
CN (1) CN106537591B (pt)
BR (1) BR112016028583B1 (pt)
DE (1) DE112015002108B4 (pt)
RU (1) RU2661979C2 (pt)
TW (1) TWI592716B (pt)
WO (1) WO2016007315A1 (pt)

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JP2020113724A (ja) 2019-01-17 2020-07-27 キオクシア株式会社 半導体装置
JP2021034486A (ja) * 2019-08-21 2021-03-01 キオクシア株式会社 半導体記憶装置
US11296101B2 (en) 2020-03-27 2022-04-05 Sandisk Technologies Llc Three-dimensional memory device including an inter-tier etch stop layer and method of making the same
KR102374588B1 (ko) * 2020-05-13 2022-03-14 경희대학교 산학협력단 3차원 반도체 장치 및 이의 제조 방법
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Also Published As

Publication number Publication date
US9595531B2 (en) 2017-03-14
JP6442735B2 (ja) 2018-12-26
DE112015002108B4 (de) 2020-01-02
BR112016028583B1 (pt) 2022-09-20
EP3172766A4 (en) 2018-02-28
WO2016007315A1 (en) 2016-01-14
KR20170003658A (ko) 2017-01-09
DE112015002108T5 (de) 2017-03-02
CN106537591B (zh) 2019-09-17
US20170140941A1 (en) 2017-05-18
RU2016148254A (ru) 2018-06-09
RU2016148254A3 (pt) 2018-06-09
CN106537591A (zh) 2017-03-22
TW201606388A (zh) 2016-02-16
US10002767B2 (en) 2018-06-19
US20160133640A1 (en) 2016-05-12
JP2017518643A (ja) 2017-07-06
EP3172766A1 (en) 2017-05-31
RU2661979C2 (ru) 2018-07-23
TWI592716B (zh) 2017-07-21
KR102219033B1 (ko) 2021-02-23

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Legal Events

Date Code Title Description
B15K Others concerning applications: alteration of classification

Ipc: H01L 27/115 (2017.01), H01L 21/00 (2006.01)

B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 26/06/2015, OBSERVADAS AS CONDICOES LEGAIS