BR112016024898A2 - estrutura de potência escalonada em uma rede de distribuição de potência (pdn) - Google Patents

estrutura de potência escalonada em uma rede de distribuição de potência (pdn)

Info

Publication number
BR112016024898A2
BR112016024898A2 BR112016024898A BR112016024898A BR112016024898A2 BR 112016024898 A2 BR112016024898 A2 BR 112016024898A2 BR 112016024898 A BR112016024898 A BR 112016024898A BR 112016024898 A BR112016024898 A BR 112016024898A BR 112016024898 A2 BR112016024898 A2 BR 112016024898A2
Authority
BR
Brazil
Prior art keywords
pdn
regions
metal layer
distribution network
integrated device
Prior art date
Application number
BR112016024898A
Other languages
English (en)
Portuguese (pt)
Inventor
David Paynter Charles
Kae Zang Ruey
David Lane Ryan
Li Yue
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112016024898A2 publication Critical patent/BR112016024898A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0224—Patterned shielding planes, ground planes or power planes
    • H05K1/0225—Single or multiple openings in a shielding, ground or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0236—Electromagnetic band-gap structures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0091—Apparatus for coating printed circuits using liquid non-metallic coating compositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structure Of Printed Boards (AREA)
BR112016024898A 2014-04-29 2015-04-28 estrutura de potência escalonada em uma rede de distribuição de potência (pdn) BR112016024898A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/264,836 US10231324B2 (en) 2014-04-29 2014-04-29 Staggered power structure in a power distribution network (PDN)
PCT/US2015/028061 WO2015168160A1 (en) 2014-04-29 2015-04-28 Staggered power structure in a power distribution network (pdn)

Publications (1)

Publication Number Publication Date
BR112016024898A2 true BR112016024898A2 (pt) 2017-08-15

Family

ID=53175170

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112016024898A BR112016024898A2 (pt) 2014-04-29 2015-04-28 estrutura de potência escalonada em uma rede de distribuição de potência (pdn)

Country Status (7)

Country Link
US (1) US10231324B2 (https=)
EP (1) EP3138127B1 (https=)
JP (1) JP2017515305A (https=)
KR (1) KR20160146751A (https=)
CN (1) CN106256020B (https=)
BR (1) BR112016024898A2 (https=)
WO (1) WO2015168160A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101933408B1 (ko) * 2015-11-10 2018-12-28 삼성전기 주식회사 전자부품 패키지 및 이를 포함하는 전자기기
KR102410661B1 (ko) 2015-11-13 2022-06-20 삼성디스플레이 주식회사 터치 패널 및 이를 포함하는 표시 장치
IT202000029210A1 (it) * 2020-12-01 2022-06-01 St Microelectronics Srl Dispositivo a semiconduttore e corrispondente procedimento
CN113741728B (zh) * 2021-08-19 2023-11-28 武汉华星光电半导体显示技术有限公司 触控面板和移动终端

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3432963B2 (ja) 1995-06-15 2003-08-04 沖電気工業株式会社 半導体集積回路
US6484302B1 (en) 2000-07-11 2002-11-19 Hewlett-Packard Company Auto-contactor system and method for generating variable size contacts
US6495770B2 (en) * 2000-12-04 2002-12-17 Intel Corporation Electronic assembly providing shunting of electrical current
US6609242B1 (en) 2001-07-20 2003-08-19 Hewlett-Packard Development Company, L.P. Automated creation of power distribution grids for tiled cell arrays in integrated circuit designs
US6891260B1 (en) * 2002-06-06 2005-05-10 Lsi Logic Corporation Integrated circuit package substrate with high density routing mechanism
US6978433B1 (en) 2002-09-16 2005-12-20 Xilinx, Inc. Method and apparatus for placement of vias
US7089522B2 (en) 2003-06-11 2006-08-08 Chartered Semiconductor Manufacturing, Ltd. Device, design and method for a slot in a conductive area
US7237218B2 (en) * 2004-08-26 2007-06-26 Lsi Corporation Optimizing dynamic power characteristics of an integrated circuit chip
US7294791B2 (en) * 2004-09-29 2007-11-13 Endicott Interconnect Technologies, Inc. Circuitized substrate with improved impedance control circuitry, method of making same, electrical assembly and information handling system utilizing same
US8159413B2 (en) * 2006-11-01 2012-04-17 Agency For Science, Technology And Research Double-stacked EBG structure
JP5433972B2 (ja) * 2008-04-21 2014-03-05 日本電気株式会社 半導体装置及びその製造方法
US8230375B2 (en) 2008-09-14 2012-07-24 Raminda Udaya Madurawe Automated metal pattern generation for integrated circuits
US8106504B2 (en) * 2008-09-25 2012-01-31 King Dragon International Inc. Stacking package structure with chip embedded inside and die having through silicon via and method of the same
US8330489B2 (en) 2009-04-28 2012-12-11 International Business Machines Corporation Universal inter-layer interconnect for multi-layer semiconductor stacks
JP5581795B2 (ja) 2010-05-07 2014-09-03 ルネサスエレクトロニクス株式会社 スタンダードセル、スタンダードセルを備えた半導体装置、およびスタンダードセルの配置配線方法
WO2012041889A1 (en) 2010-09-29 2012-04-05 St-Ericsson Sa Power routing with integrated decoupling capacitance
US8975670B2 (en) * 2011-03-06 2015-03-10 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US8749322B2 (en) * 2011-09-02 2014-06-10 National Taiwan University Multilayer circuit board structure and circuitry thereof
US20170017744A1 (en) * 2015-07-15 2017-01-19 E-System Design, Inc. Modeling of Power Distribution Networks for Path Finding

Also Published As

Publication number Publication date
EP3138127B1 (en) 2023-01-04
WO2015168160A1 (en) 2015-11-05
EP3138127A1 (en) 2017-03-08
US20150313006A1 (en) 2015-10-29
US10231324B2 (en) 2019-03-12
JP2017515305A (ja) 2017-06-08
CN106256020A (zh) 2016-12-21
KR20160146751A (ko) 2016-12-21
CN106256020B (zh) 2019-03-22

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 5A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2564 DE 2020-02-27

B350 Update of information on the portal [chapter 15.35 patent gazette]