BR112014011806B1 - memória configurada para prover acesso de leitura/gravação simultânea para múltiplos bancos - Google Patents

memória configurada para prover acesso de leitura/gravação simultânea para múltiplos bancos Download PDF

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Publication number
BR112014011806B1
BR112014011806B1 BR112014011806-0A BR112014011806A BR112014011806B1 BR 112014011806 B1 BR112014011806 B1 BR 112014011806B1 BR 112014011806 A BR112014011806 A BR 112014011806A BR 112014011806 B1 BR112014011806 B1 BR 112014011806B1
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BR
Brazil
Prior art keywords
memory
controller
memory address
local
read
Prior art date
Application number
BR112014011806-0A
Other languages
English (en)
Portuguese (pt)
Other versions
BR112014011806A2 (pt
Inventor
Esin Terzioglu
Dongkyu Park
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of BR112014011806A2 publication Critical patent/BR112014011806A2/pt
Publication of BR112014011806B1 publication Critical patent/BR112014011806B1/pt

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
BR112014011806-0A 2011-11-16 2012-11-16 memória configurada para prover acesso de leitura/gravação simultânea para múltiplos bancos BR112014011806B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/297,771 2011-11-16
US13/297,771 US8699277B2 (en) 2011-11-16 2011-11-16 Memory configured to provide simultaneous read/write access to multiple banks
PCT/US2012/065658 WO2013075013A1 (en) 2011-11-16 2012-11-16 Memory configured to provide simultaneous read/write access to multiple banks

Publications (2)

Publication Number Publication Date
BR112014011806A2 BR112014011806A2 (pt) 2017-05-16
BR112014011806B1 true BR112014011806B1 (pt) 2021-01-26

Family

ID=47470109

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112014011806-0A BR112014011806B1 (pt) 2011-11-16 2012-11-16 memória configurada para prover acesso de leitura/gravação simultânea para múltiplos bancos

Country Status (10)

Country Link
US (1) US8699277B2 (https=)
EP (2) EP3082048B1 (https=)
JP (1) JP5852259B2 (https=)
KR (1) KR101669945B1 (https=)
CN (1) CN104081372B (https=)
BR (1) BR112014011806B1 (https=)
ES (2) ES2700854T3 (https=)
HU (1) HUE028961T2 (https=)
IN (1) IN2014CN03730A (https=)
WO (1) WO2013075013A1 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013014841A1 (ja) * 2011-07-22 2013-01-31 パナソニック株式会社 データ処理装置およびデータ処理方法
US10719237B2 (en) 2016-01-11 2020-07-21 Micron Technology, Inc. Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory
US10140044B2 (en) * 2016-03-31 2018-11-27 Qualcomm Incorporated Efficient memory bank design
US11294594B2 (en) * 2017-08-07 2022-04-05 Kioxia Corporation SSD architecture supporting low latency operation
US11113006B2 (en) 2019-05-06 2021-09-07 Micron Technology, Inc. Dynamic data placement for collision avoidance among concurrent write streams
US11113198B2 (en) 2019-05-06 2021-09-07 Micron Technology, Inc. Timed data transfer between a host system and a memory sub-system
US11776591B2 (en) * 2019-09-26 2023-10-03 Arm Limited Concurrent access techniques utilizing wordlines with the same row address in single port memory
US11386937B2 (en) 2019-10-12 2022-07-12 Arm Limited System device and method for providing single port memory access in bitcell array by tracking dummy wordline

Family Cites Families (22)

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KR0145224B1 (ko) 1995-05-27 1998-08-17 김광호 불휘발성 반도체 메모리의 분리된 기입 및 독출 경로를 가지는 워드라인 구동회로
US5996051A (en) 1997-04-14 1999-11-30 Advanced Micro Devices, Inc. Communication system which in a first mode supports concurrent memory acceses of a partitioned memory array and in a second mode supports non-concurrent memory accesses to the entire memory array
US6009501A (en) * 1997-06-18 1999-12-28 Micron Technology, Inc. Method and apparatus for local control signal generation in a memory device
CA2239426A1 (en) 1998-06-03 1999-12-03 Newbridge Networks Corporation Shared memory system
JP2000276400A (ja) * 1999-03-25 2000-10-06 Univ Hiroshima アドレス及びデータ転送回路
US6412030B1 (en) 1999-04-16 2002-06-25 Koninklijke Philips Electronics N.V. System and method to optimize read performance while accepting write data in a PCI bus architecture
CN1282925A (zh) * 1999-07-12 2001-02-07 松下电器产业株式会社 数据处理装置
US6377492B1 (en) 2001-03-19 2002-04-23 Etron Technologies, Inc. Memory architecture for read and write at the same time using a conventional cell
US7738496B1 (en) 2002-12-31 2010-06-15 Cypress Semiconductor Corporation Device that provides the functionality of dual-ported memory using single-ported memory for multiple clock domains
JP4413524B2 (ja) * 2003-05-01 2010-02-10 株式会社東芝 マルチポートメモリ
JP2005242929A (ja) * 2004-02-27 2005-09-08 Fujitsu Ltd 共有メモリのアクセス方法及びデータ処理装置
US20070028027A1 (en) 2005-07-26 2007-02-01 Micron Technology, Inc. Memory device and method having separate write data and read data buses
US7533222B2 (en) 2006-06-29 2009-05-12 Mosys, Inc. Dual-port SRAM memory using single-port memory cell
JP4205743B2 (ja) * 2006-08-22 2009-01-07 エルピーダメモリ株式会社 半導体記憶装置及び半導体装置
US7523228B2 (en) * 2006-09-18 2009-04-21 International Business Machines Corporation Method for performing a direct memory access block move in a direct memory access device
US7551512B2 (en) 2007-07-30 2009-06-23 Agere Systems Inc. Dual-port memory
US7739433B2 (en) 2008-03-05 2010-06-15 Microchip Technology Incorporated Sharing bandwidth of a single port SRAM between at least one DMA peripheral and a CPU operating with a quadrature clock
US7760562B2 (en) 2008-03-13 2010-07-20 Qualcomm Incorporated Address multiplexing in pseudo-dual port memory
US8140739B2 (en) * 2008-08-08 2012-03-20 Imation Corp. Flash memory based storage devices utilizing magnetoresistive random access memory (MRAM) to store files having logical block addresses stored in a write frequency file buffer table
US8164974B2 (en) * 2009-02-24 2012-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuits, systems, and method of interleaving accesses thereof
US8331123B2 (en) * 2009-09-21 2012-12-11 Ocz Technology Group, Inc. High performance solid-state drives and methods therefor
US8375173B2 (en) * 2009-10-09 2013-02-12 Qualcomm Incorporated Accessing a multi-channel memory system having non-uniform page sizes

Also Published As

Publication number Publication date
EP3082048A1 (en) 2016-10-19
US8699277B2 (en) 2014-04-15
EP2780813B1 (en) 2016-04-06
ES2700854T3 (es) 2019-02-19
CN104081372A (zh) 2014-10-01
US20130121086A1 (en) 2013-05-16
JP2014533861A (ja) 2014-12-15
EP3082048B1 (en) 2018-10-03
EP2780813A1 (en) 2014-09-24
HUE028961T2 (en) 2017-02-28
KR101669945B1 (ko) 2016-10-27
IN2014CN03730A (https=) 2015-07-03
CN104081372B (zh) 2017-06-13
WO2013075013A1 (en) 2013-05-23
JP5852259B2 (ja) 2016-02-03
BR112014011806A2 (pt) 2017-05-16
KR20140098792A (ko) 2014-08-08
ES2575095T3 (es) 2016-06-24

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Legal Events

Date Code Title Description
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 16/11/2012, OBSERVADAS AS CONDICOES LEGAIS.