ES2700854T3 - Memoria configurada para proporcionar acceso simultáneo de lectura/escritura a múltiples bancos - Google Patents
Memoria configurada para proporcionar acceso simultáneo de lectura/escritura a múltiples bancos Download PDFInfo
- Publication number
- ES2700854T3 ES2700854T3 ES16160755T ES16160755T ES2700854T3 ES 2700854 T3 ES2700854 T3 ES 2700854T3 ES 16160755 T ES16160755 T ES 16160755T ES 16160755 T ES16160755 T ES 16160755T ES 2700854 T3 ES2700854 T3 ES 2700854T3
- Authority
- ES
- Spain
- Prior art keywords
- memory
- read
- controller
- write
- local
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1663—Access to shared memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Static Random-Access Memory (AREA)
- Read Only Memory (AREA)
- Dram (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Memory System (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/297,771 US8699277B2 (en) | 2011-11-16 | 2011-11-16 | Memory configured to provide simultaneous read/write access to multiple banks |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ES2700854T3 true ES2700854T3 (es) | 2019-02-19 |
Family
ID=47470109
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES16160755T Active ES2700854T3 (es) | 2011-11-16 | 2012-11-16 | Memoria configurada para proporcionar acceso simultáneo de lectura/escritura a múltiples bancos |
| ES12808934.9T Active ES2575095T3 (es) | 2011-11-16 | 2012-11-16 | Memoria configurada para proporcionar acceso simultáneo de lectura / escritura a múltiples bancos |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES12808934.9T Active ES2575095T3 (es) | 2011-11-16 | 2012-11-16 | Memoria configurada para proporcionar acceso simultáneo de lectura / escritura a múltiples bancos |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US8699277B2 (https=) |
| EP (2) | EP3082048B1 (https=) |
| JP (1) | JP5852259B2 (https=) |
| KR (1) | KR101669945B1 (https=) |
| CN (1) | CN104081372B (https=) |
| BR (1) | BR112014011806B1 (https=) |
| ES (2) | ES2700854T3 (https=) |
| HU (1) | HUE028961T2 (https=) |
| IN (1) | IN2014CN03730A (https=) |
| WO (1) | WO2013075013A1 (https=) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013014841A1 (ja) * | 2011-07-22 | 2013-01-31 | パナソニック株式会社 | データ処理装置およびデータ処理方法 |
| US10719237B2 (en) | 2016-01-11 | 2020-07-21 | Micron Technology, Inc. | Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory |
| US10140044B2 (en) * | 2016-03-31 | 2018-11-27 | Qualcomm Incorporated | Efficient memory bank design |
| US11294594B2 (en) * | 2017-08-07 | 2022-04-05 | Kioxia Corporation | SSD architecture supporting low latency operation |
| US11113006B2 (en) | 2019-05-06 | 2021-09-07 | Micron Technology, Inc. | Dynamic data placement for collision avoidance among concurrent write streams |
| US11113198B2 (en) | 2019-05-06 | 2021-09-07 | Micron Technology, Inc. | Timed data transfer between a host system and a memory sub-system |
| US11776591B2 (en) * | 2019-09-26 | 2023-10-03 | Arm Limited | Concurrent access techniques utilizing wordlines with the same row address in single port memory |
| US11386937B2 (en) | 2019-10-12 | 2022-07-12 | Arm Limited | System device and method for providing single port memory access in bitcell array by tracking dummy wordline |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0145224B1 (ko) | 1995-05-27 | 1998-08-17 | 김광호 | 불휘발성 반도체 메모리의 분리된 기입 및 독출 경로를 가지는 워드라인 구동회로 |
| US5996051A (en) | 1997-04-14 | 1999-11-30 | Advanced Micro Devices, Inc. | Communication system which in a first mode supports concurrent memory acceses of a partitioned memory array and in a second mode supports non-concurrent memory accesses to the entire memory array |
| US6009501A (en) * | 1997-06-18 | 1999-12-28 | Micron Technology, Inc. | Method and apparatus for local control signal generation in a memory device |
| CA2239426A1 (en) | 1998-06-03 | 1999-12-03 | Newbridge Networks Corporation | Shared memory system |
| JP2000276400A (ja) * | 1999-03-25 | 2000-10-06 | Univ Hiroshima | アドレス及びデータ転送回路 |
| US6412030B1 (en) | 1999-04-16 | 2002-06-25 | Koninklijke Philips Electronics N.V. | System and method to optimize read performance while accepting write data in a PCI bus architecture |
| CN1282925A (zh) * | 1999-07-12 | 2001-02-07 | 松下电器产业株式会社 | 数据处理装置 |
| US6377492B1 (en) | 2001-03-19 | 2002-04-23 | Etron Technologies, Inc. | Memory architecture for read and write at the same time using a conventional cell |
| US7738496B1 (en) | 2002-12-31 | 2010-06-15 | Cypress Semiconductor Corporation | Device that provides the functionality of dual-ported memory using single-ported memory for multiple clock domains |
| JP4413524B2 (ja) * | 2003-05-01 | 2010-02-10 | 株式会社東芝 | マルチポートメモリ |
| JP2005242929A (ja) * | 2004-02-27 | 2005-09-08 | Fujitsu Ltd | 共有メモリのアクセス方法及びデータ処理装置 |
| US20070028027A1 (en) | 2005-07-26 | 2007-02-01 | Micron Technology, Inc. | Memory device and method having separate write data and read data buses |
| US7533222B2 (en) | 2006-06-29 | 2009-05-12 | Mosys, Inc. | Dual-port SRAM memory using single-port memory cell |
| JP4205743B2 (ja) * | 2006-08-22 | 2009-01-07 | エルピーダメモリ株式会社 | 半導体記憶装置及び半導体装置 |
| US7523228B2 (en) * | 2006-09-18 | 2009-04-21 | International Business Machines Corporation | Method for performing a direct memory access block move in a direct memory access device |
| US7551512B2 (en) | 2007-07-30 | 2009-06-23 | Agere Systems Inc. | Dual-port memory |
| US7739433B2 (en) | 2008-03-05 | 2010-06-15 | Microchip Technology Incorporated | Sharing bandwidth of a single port SRAM between at least one DMA peripheral and a CPU operating with a quadrature clock |
| US7760562B2 (en) | 2008-03-13 | 2010-07-20 | Qualcomm Incorporated | Address multiplexing in pseudo-dual port memory |
| US8140739B2 (en) * | 2008-08-08 | 2012-03-20 | Imation Corp. | Flash memory based storage devices utilizing magnetoresistive random access memory (MRAM) to store files having logical block addresses stored in a write frequency file buffer table |
| US8164974B2 (en) * | 2009-02-24 | 2012-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuits, systems, and method of interleaving accesses thereof |
| US8331123B2 (en) * | 2009-09-21 | 2012-12-11 | Ocz Technology Group, Inc. | High performance solid-state drives and methods therefor |
| US8375173B2 (en) * | 2009-10-09 | 2013-02-12 | Qualcomm Incorporated | Accessing a multi-channel memory system having non-uniform page sizes |
-
2011
- 2011-11-16 US US13/297,771 patent/US8699277B2/en active Active
-
2012
- 2012-11-16 ES ES16160755T patent/ES2700854T3/es active Active
- 2012-11-16 BR BR112014011806-0A patent/BR112014011806B1/pt active IP Right Grant
- 2012-11-16 CN CN201280066367.2A patent/CN104081372B/zh active Active
- 2012-11-16 EP EP16160755.1A patent/EP3082048B1/en active Active
- 2012-11-16 HU HUE12808934A patent/HUE028961T2/en unknown
- 2012-11-16 EP EP12808934.9A patent/EP2780813B1/en active Active
- 2012-11-16 IN IN3730CHN2014 patent/IN2014CN03730A/en unknown
- 2012-11-16 WO PCT/US2012/065658 patent/WO2013075013A1/en not_active Ceased
- 2012-11-16 KR KR1020147016345A patent/KR101669945B1/ko active Active
- 2012-11-16 JP JP2014542515A patent/JP5852259B2/ja active Active
- 2012-11-16 ES ES12808934.9T patent/ES2575095T3/es active Active
Also Published As
| Publication number | Publication date |
|---|---|
| EP3082048A1 (en) | 2016-10-19 |
| US8699277B2 (en) | 2014-04-15 |
| EP2780813B1 (en) | 2016-04-06 |
| BR112014011806B1 (pt) | 2021-01-26 |
| CN104081372A (zh) | 2014-10-01 |
| US20130121086A1 (en) | 2013-05-16 |
| JP2014533861A (ja) | 2014-12-15 |
| EP3082048B1 (en) | 2018-10-03 |
| EP2780813A1 (en) | 2014-09-24 |
| HUE028961T2 (en) | 2017-02-28 |
| KR101669945B1 (ko) | 2016-10-27 |
| IN2014CN03730A (https=) | 2015-07-03 |
| CN104081372B (zh) | 2017-06-13 |
| WO2013075013A1 (en) | 2013-05-23 |
| JP5852259B2 (ja) | 2016-02-03 |
| BR112014011806A2 (pt) | 2017-05-16 |
| KR20140098792A (ko) | 2014-08-08 |
| ES2575095T3 (es) | 2016-06-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| ES2700854T3 (es) | Memoria configurada para proporcionar acceso simultáneo de lectura/escritura a múltiples bancos | |
| ES2540058T3 (es) | Multiplexado de direcciones en una memoria de puerto pseudo-dual | |
| US8374050B2 (en) | Multi-port memory using single-port memory cells | |
| US8977811B2 (en) | Scalable schedulers for memory controllers | |
| JP2007504530A (ja) | 複数のメモリハブモジュールを含むマルチプロセッサシステムおよびその方法 | |
| US7349285B2 (en) | Dual port memory unit using a single port memory core | |
| ES2847228T3 (es) | Decodificación separada de direcciones de lectura y escritura en un sistema de memoria para admitir operaciones simultáneas de lectura y escritura de memoria | |
| JPH1031886A (ja) | ランダムアクセスメモリ | |
| US9390017B2 (en) | Write and read collision avoidance in single port memory devices | |
| US9208856B2 (en) | Multiport memory with matching address control | |
| US8995210B1 (en) | Write and read collision avoidance in single port memory devices | |
| US20100232238A1 (en) | Dual port memory device, memory device and method of operating the dual port memory device | |
| US20170075571A1 (en) | Memory device and control method thereof | |
| US9158715B1 (en) | Multi-input memory command prioritization | |
| US8848480B1 (en) | Synchronous multiple port memory with asynchronous ports | |
| KR20050079862A (ko) | 접근 금지 신호를 갖는 듀얼 포트 메모리 장치 | |
| US8074096B2 (en) | Semiconductor integrated circuit, memory system, memory controller and memory control method | |
| CN103928049B (zh) | 带有匹配地址控制的多端口存储器 | |
| JP2010049511A (ja) | 共有メモリへのアクセス方式およびマルチｃｐｕ構成のプログラマブルコントローラ | |
| KR100827720B1 (ko) | 접근 제어 장치를 가지는 듀얼 포트 메모리, 듀얼 포트메모리를 가지는 메모리 시스템 및 듀얼 포트 메모리의접근 제어 방법 | |
| US12333150B1 (en) | Partitioned non-volatile memory (NVM) having a normal read bus and a verify read bus | |
| US20060248247A1 (en) | Apparatus and method for controlling access to a memory | |
| US20170220497A1 (en) | System and method for operating the same | |
| US20180053541A1 (en) | Semiconductor memory apparatus | |
| KR20080046066A (ko) | 동기 제어 장치를 가지는 듀얼 포트 메모리, 동기 제어장치를 가지는 듀얼 포트 메모리 시스템 및 듀얼 포트메모리 시스템의 동기 제어 방법 |