BR0209971A - Processo para a fabricação de componentes para equipamentos eletrônicos - Google Patents

Processo para a fabricação de componentes para equipamentos eletrônicos

Info

Publication number
BR0209971A
BR0209971A BR0209971-3A BR0209971A BR0209971A BR 0209971 A BR0209971 A BR 0209971A BR 0209971 A BR0209971 A BR 0209971A BR 0209971 A BR0209971 A BR 0209971A
Authority
BR
Brazil
Prior art keywords
layer
metal foil
substrate material
coating
electronic equipment
Prior art date
Application number
BR0209971-3A
Other languages
English (en)
Inventor
Anders V Ekman
Richard Stoessel
Thierry Becret
Thierry Tschan
Kurt Stutz
Original Assignee
Vantico Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vantico Ag filed Critical Vantico Ag
Publication of BR0209971A publication Critical patent/BR0209971A/pt

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H05K3/4655—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern by using a laminate characterized by the insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0756—Uses of liquids, e.g. rinsing, coating, dissolving
    • H05K2203/0759—Forming a polymer layer by liquid coating, e.g. a non-metallic protective coating or an organic bonding layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Laminated Bodies (AREA)
  • Application Of Or Painting With Fluid Materials (AREA)
  • Epoxy Resins (AREA)
  • Ceramic Capacitors (AREA)
  • Magnetic Ceramics (AREA)
  • Compositions Of Oxide Ceramics (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Adhesives Or Adhesive Processes (AREA)

Abstract

"PROCESSO PARA A FABRICAçãO DE COMPONENTES PARA EQUIPAMENTOS ELETRôNICOS". Processo para a fabricação de componentes para equipamentos eletrônicos de um material de suporte plano (1) que em pelo menos uma superfície possui furos contínuos (5) e reentrâncias (4), com uma camada intermediária (6) em pelo menos uma superfície do material de suporte (1), e com uma folha de metal (8) aderente na camada (6) mencionada, abrangendo as etapas (a) revestimento de um material de suporte plano (1) com uma composição constituindo a camada intermediária (6), (b) colocação da folha de metal (8) sobre o revestimento, e (c) união das partes sob pressão e aquecimento. O processo é caracterizado pela utilização de um sistema de dois componentes líquidos, contendo um solvente e termicamente solidificável, de pelo menos um acelerador e pelo menos um composto solidificável, que é colocada como camada (6) em pelo menos uma superfície do material de suporte (1) e, depois seca. Sobre a camada (6) formada solidificada e seca é depois laminada uma folha de metal (8) sob pressão e temperatura elevada, solidificando a camada. De especial preferência, são produzidas placas de circuito impresso (7) de acordo com o processo de acordo com a presente invenção.
BR0209971-3A 2001-05-21 2002-05-15 Processo para a fabricação de componentes para equipamentos eletrônicos BR0209971A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH9442001 2001-05-21
PCT/EP2002/005348 WO2002096171A1 (de) 2001-05-21 2002-05-15 Verfahren zur herstellung von bauelementen für elektronische geräte

Publications (1)

Publication Number Publication Date
BR0209971A true BR0209971A (pt) 2004-04-06

Family

ID=4549641

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0209971-3A BR0209971A (pt) 2001-05-21 2002-05-15 Processo para a fabricação de componentes para equipamentos eletrônicos

Country Status (13)

Country Link
US (1) US20040216838A1 (pt)
EP (1) EP1389408B1 (pt)
JP (1) JP2004532116A (pt)
KR (1) KR100893716B1 (pt)
CN (1) CN1311722C (pt)
AT (1) ATE279090T1 (pt)
BR (1) BR0209971A (pt)
CA (1) CA2449198A1 (pt)
DE (1) DE50201239D1 (pt)
IL (1) IL158699A0 (pt)
NO (1) NO20035058L (pt)
RU (1) RU2003133438A (pt)
WO (1) WO2002096171A1 (pt)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7666938B2 (en) * 2004-12-03 2010-02-23 Henkel Corporation Nanoparticle silica filled benzoxazine compositions
US8029889B1 (en) 2004-12-03 2011-10-04 Henkel Corporation Prepregs, towpregs and preforms
TWI294757B (en) * 2005-07-06 2008-03-11 Delta Electronics Inc Circuit board with a through hole wire, and forming method thereof
US7404725B2 (en) * 2006-07-03 2008-07-29 Hall David R Wiper for tool string direct electrical connection
KR101750836B1 (ko) * 2015-10-14 2017-06-27 대덕전자 주식회사 캐비티 회로기판 제조방법

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH470344A (de) * 1966-12-02 1969-03-31 Ciba Geigy Verfahren zur Herstellung von neuen Addukten aus Polypoxiden und Polyaminen
US4330659A (en) * 1980-10-06 1982-05-18 Ciba-Geigy Corporation Modified amine hardener systems
US4500582A (en) * 1981-05-26 1985-02-19 Ciba-Geigy Corporation Modified amine hardener systems
US4540750A (en) * 1984-09-24 1985-09-10 Ciba-Geigy Corporation Diethyl toluene diamine hardener systems
GB8630392D0 (en) * 1986-12-19 1987-01-28 Prestwick Circuits Ltd Producing printed circuit boards
CA2006809A1 (en) * 1988-12-28 1990-06-28 Toru Shirose Laminate film having a thermosetting resin layer and use thereof for forming electrically insulating layer over conducting surface
JPH02178042A (ja) * 1988-12-28 1990-07-11 Somar Corp 熱硬化性樹脂フイルム
JPH02177596A (ja) * 1988-12-28 1990-07-10 Somar Corp 多層配線板の製造方法
DE59000858D1 (de) * 1989-01-16 1993-03-25 Ciba Geigy Ag Araliphatische sulfoniumsalze und deren verwendung.
GB2259812B (en) * 1991-09-06 1996-04-24 Toa Gosei Chem Ind Method for making multilayer printed circuit board having blind holes and resin-coated copper foil used for the method
TW237466B (pt) * 1992-07-21 1995-01-01 Giba Gerigy Ag
JPH0722741A (ja) * 1993-07-01 1995-01-24 Japan Gore Tex Inc カバーレイフィルム及びカバーレイフィルム被覆回路基板
US6016598A (en) * 1995-02-13 2000-01-25 Akzo Nobel N.V. Method of manufacturing a multilayer printed wire board
JP3084352B2 (ja) * 1995-08-28 2000-09-04 太陽インキ製造株式会社 銅箔ラミネート方式ビルドアップ用絶縁樹脂組成物とこれを用いた多層プリント配線板の製造方法
TW331698B (en) * 1996-06-18 1998-05-11 Hitachi Chemical Co Ltd Multi-layered printed circuit board
US5837355A (en) * 1996-11-07 1998-11-17 Sumitomo Bakelite Company Limited Multilayer printed circuit board and process for producing and using the same
TW399398B (en) * 1998-01-07 2000-07-21 Taiyo Ink Seizo K K Liquid thermosetting filling composition and method for permanently filling holes in printed circuit board by the use thereof

Also Published As

Publication number Publication date
US20040216838A1 (en) 2004-11-04
WO2002096171A1 (de) 2002-11-28
NO20035058D0 (no) 2003-11-13
KR100893716B1 (ko) 2009-04-17
EP1389408B1 (de) 2004-10-06
DE50201239D1 (de) 2004-11-11
ATE279090T1 (de) 2004-10-15
CA2449198A1 (en) 2002-11-28
EP1389408A1 (de) 2004-02-18
IL158699A0 (en) 2004-05-12
JP2004532116A (ja) 2004-10-21
RU2003133438A (ru) 2005-05-10
CN1311722C (zh) 2007-04-18
KR20040005957A (ko) 2004-01-16
CN1511434A (zh) 2004-07-07
NO20035058L (no) 2003-11-13

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Legal Events

Date Code Title Description
B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B11Y Definitive dismissal - extension of time limit for request of examination expired [chapter 11.1.1 patent gazette]