AU2003297025A1 - Fast localization of electrical failures on an integrated circuit system and method - Google Patents

Fast localization of electrical failures on an integrated circuit system and method

Info

Publication number
AU2003297025A1
AU2003297025A1 AU2003297025A AU2003297025A AU2003297025A1 AU 2003297025 A1 AU2003297025 A1 AU 2003297025A1 AU 2003297025 A AU2003297025 A AU 2003297025A AU 2003297025 A AU2003297025 A AU 2003297025A AU 2003297025 A1 AU2003297025 A1 AU 2003297025A1
Authority
AU
Australia
Prior art keywords
integrated circuit
circuit system
electrical failures
fast localization
localization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003297025A
Other languages
English (en)
Other versions
AU2003297025A8 (en
Inventor
Dennis Ciplickas
Christopher Hess
Sherry Lee
Larg H. Weiland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PDF Solutions Inc
Original Assignee
PDF Solutions Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PDF Solutions Inc filed Critical PDF Solutions Inc
Publication of AU2003297025A1 publication Critical patent/AU2003297025A1/en
Publication of AU2003297025A8 publication Critical patent/AU2003297025A8/xx
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2884Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27Structural arrangements therefor
    • H10P74/277Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2894Aspects of quality control [QC]
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302Contactless testing
    • G01R31/305Contactless testing using electron beams
    • G01R31/307Contactless testing using electron beams of integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)
AU2003297025A 2002-12-11 2003-12-11 Fast localization of electrical failures on an integrated circuit system and method Abandoned AU2003297025A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US43278602P 2002-12-11 2002-12-11
US60/432,786 2002-12-11
PCT/US2003/039698 WO2004053944A2 (en) 2002-12-11 2003-12-11 Fast localization of electrical failures on an integrated circuit system and method

Publications (2)

Publication Number Publication Date
AU2003297025A1 true AU2003297025A1 (en) 2004-06-30
AU2003297025A8 AU2003297025A8 (en) 2004-06-30

Family

ID=32507992

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003297025A Abandoned AU2003297025A1 (en) 2002-12-11 2003-12-11 Fast localization of electrical failures on an integrated circuit system and method

Country Status (6)

Country Link
US (1) US7527987B2 (https=)
EP (1) EP1570510A2 (https=)
JP (1) JP2006515464A (https=)
CN (1) CN1723544A (https=)
AU (1) AU2003297025A1 (https=)
WO (1) WO2004053944A2 (https=)

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US10199283B1 (en) 2015-02-03 2019-02-05 Pdf Solutions, Inc. Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage
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US10978438B1 (en) 2015-12-16 2021-04-13 Pdf Solutions, Inc. IC with test structures and E-beam pads embedded within a contiguous standard cell area
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US9929063B1 (en) 2016-04-04 2018-03-27 Pdf Solutions, Inc. Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
TWI598610B (zh) * 2017-02-16 2017-09-11 致茂電子股份有限公司 通用控制系統
US9748153B1 (en) 2017-03-29 2017-08-29 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configure
US9773774B1 (en) 2017-03-30 2017-09-26 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells
US9768083B1 (en) 2017-06-27 2017-09-19 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
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US9865583B1 (en) 2017-06-28 2018-01-09 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells
US10096530B1 (en) 2017-06-28 2018-10-09 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells
CN107861045A (zh) * 2017-10-13 2018-03-30 天津市英贝特航天科技有限公司 一种基于直流ct技术的短路芯片查找装置及方法
US10970834B2 (en) * 2018-01-05 2021-04-06 Kla-Tencor Corporation Defect discovery using electron beam inspection and deep learning with real-time intelligence to reduce nuisance
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KR102925871B1 (ko) * 2022-05-03 2026-02-10 삼성디스플레이 주식회사 표시 장치의 검사 방법 및 표시 장치의 검사 장치

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Also Published As

Publication number Publication date
US7527987B2 (en) 2009-05-05
AU2003297025A8 (en) 2004-06-30
WO2004053944A2 (en) 2004-06-24
US20060105475A1 (en) 2006-05-18
CN1723544A (zh) 2006-01-18
JP2006515464A (ja) 2006-05-25
WO2004053944A3 (en) 2004-11-04
EP1570510A2 (en) 2005-09-07

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase