AU2003280621A1 - Alloy material for semiconductor, semiconductor chip using such alloy material, and method for manufacturing same - Google Patents

Alloy material for semiconductor, semiconductor chip using such alloy material, and method for manufacturing same

Info

Publication number
AU2003280621A1
AU2003280621A1 AU2003280621A AU2003280621A AU2003280621A1 AU 2003280621 A1 AU2003280621 A1 AU 2003280621A1 AU 2003280621 A AU2003280621 A AU 2003280621A AU 2003280621 A AU2003280621 A AU 2003280621A AU 2003280621 A1 AU2003280621 A1 AU 2003280621A1
Authority
AU
Australia
Prior art keywords
alloy material
semiconductor
manufacturing same
semiconductor chip
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003280621A
Other languages
English (en)
Other versions
AU2003280621A8 (en
Inventor
Kazunori Inoue
Chiharu Ishikura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Kikinzoku Kogyo KK
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of AU2003280621A1 publication Critical patent/AU2003280621A1/en
Publication of AU2003280621A8 publication Critical patent/AU2003280621A8/xx
Abandoned legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C5/00Alloys based on noble metals
    • C22C5/02Alloys based on gold
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/43Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physical Vapour Deposition (AREA)
AU2003280621A 2002-11-26 2003-10-29 Alloy material for semiconductor, semiconductor chip using such alloy material, and method for manufacturing same Abandoned AU2003280621A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2002342797A JP2004179327A (ja) 2002-11-26 2002-11-26 半導体用合金材料、該合金材料を用いた半導体チップ及びその製造方法
JP2002-342797 2002-11-26
PCT/JP2003/013890 WO2004049415A1 (ja) 2002-11-26 2003-10-29 半導体用合金材料、該合金材料を用いた半導体チップ及びその製造方法

Publications (2)

Publication Number Publication Date
AU2003280621A1 true AU2003280621A1 (en) 2004-06-18
AU2003280621A8 AU2003280621A8 (en) 2004-06-18

Family

ID=32375901

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003280621A Abandoned AU2003280621A1 (en) 2002-11-26 2003-10-29 Alloy material for semiconductor, semiconductor chip using such alloy material, and method for manufacturing same

Country Status (7)

Country Link
US (1) US20060226546A1 (enExample)
JP (1) JP2004179327A (enExample)
KR (1) KR100742672B1 (enExample)
CN (1) CN100386848C (enExample)
AU (1) AU2003280621A1 (enExample)
TW (1) TW200416748A (enExample)
WO (1) WO2004049415A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101578728B (zh) * 2006-12-21 2012-05-23 株式会社神户制钢所 燃料电池的金属隔板用合金皮膜、其制造方法和溅射用靶材、以及金属隔板和燃料电池
JP4176133B1 (ja) * 2007-06-06 2008-11-05 田中貴金属工業株式会社 プローブピン
JP5116101B2 (ja) * 2007-06-28 2013-01-09 新日鉄住金マテリアルズ株式会社 半導体実装用ボンディングワイヤ及びその製造方法
DE102014111895A1 (de) * 2014-08-20 2016-02-25 Infineon Technologies Ag Metallisierte elektrische Komponente

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3770496A (en) * 1971-06-25 1973-11-06 Du Pont Elimination of dielectric degradation in printed bold/dielectric/palladium-silver structures
JPS54144870A (en) * 1978-05-04 1979-11-12 Mitsubishi Electric Corp Wire bonding method for semiconductor element
JPS60254761A (ja) * 1984-05-31 1985-12-16 Sumitomo Electric Ind Ltd 半導体装置用リ−ドフレ−ム
JPS6173326A (ja) * 1984-09-19 1986-04-15 Hitachi Ltd 半導体装置の製造方法
JPH03155134A (ja) * 1989-11-13 1991-07-03 Seiko Epson Corp 集積回路装置の配線電極
US5364706A (en) * 1990-07-20 1994-11-15 Tanaka Denshi Kogyo Kabushiki Kaisha Clad bonding wire for semiconductor device
JPH05109818A (ja) * 1991-10-16 1993-04-30 Hitachi Chem Co Ltd 半導体チツプの接続構造
DE69333966T2 (de) * 1992-08-27 2006-09-14 Kabushiki Kaisha Toshiba, Kawasaki Elektronisches Bauteil mit metallischen Leiterbahnen und Verfahren zu seiner Herstellung
JPH118341A (ja) * 1997-06-18 1999-01-12 Mitsui High Tec Inc 半導体装置用リードフレーム
JPH11233783A (ja) * 1998-02-17 1999-08-27 Sharp Corp 薄膜トランジスタおよびその製造方法
WO2002023618A1 (en) * 2000-09-18 2002-03-21 Nippon Steel Corporation Bonding wire for semiconductor and method of manufacturing the bonding wire
JP3707548B2 (ja) * 2002-03-12 2005-10-19 株式会社三井ハイテック リードフレーム及びリードフレームの製造方法

Also Published As

Publication number Publication date
US20060226546A1 (en) 2006-10-12
CN100386848C (zh) 2008-05-07
WO2004049415A1 (ja) 2004-06-10
TW200416748A (en) 2004-09-01
JP2004179327A (ja) 2004-06-24
KR100742672B1 (ko) 2007-07-25
CN1717783A (zh) 2006-01-04
KR20050088086A (ko) 2005-09-01
TWI304220B (enExample) 2008-12-11
AU2003280621A8 (en) 2004-06-18

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase