AU2003247786A1 - High-definition de-interlacing and frame doubling circuit and method - Google Patents

High-definition de-interlacing and frame doubling circuit and method

Info

Publication number
AU2003247786A1
AU2003247786A1 AU2003247786A AU2003247786A AU2003247786A1 AU 2003247786 A1 AU2003247786 A1 AU 2003247786A1 AU 2003247786 A AU2003247786 A AU 2003247786A AU 2003247786 A AU2003247786 A AU 2003247786A AU 2003247786 A1 AU2003247786 A1 AU 2003247786A1
Authority
AU
Australia
Prior art keywords
interlacing
definition
doubling circuit
frame doubling
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003247786A
Other languages
English (en)
Inventor
Eric Stephen Carlsgaard
Michael Evan Crabb
David Leon Simpson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thomson Licensing SAS
Original Assignee
Thomson Licensing SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing SAS filed Critical Thomson Licensing SAS
Publication of AU2003247786A1 publication Critical patent/AU2003247786A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
    • H04N7/0132—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter the field or frame frequency of the incoming video signal being multiplied by a positive integer, e.g. for flicker reduction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
    • H04N7/012—Conversion between an interlaced and a progressive signal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S348/00—Television
    • Y10S348/911—Line doubler adapted for reproducing program originally from film, e.g. 24 frame per second

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Graphics (AREA)
  • Television Systems (AREA)
AU2003247786A 2002-07-05 2003-07-02 High-definition de-interlacing and frame doubling circuit and method Abandoned AU2003247786A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/190,282 US6894726B2 (en) 2002-07-05 2002-07-05 High-definition de-interlacing and frame doubling circuit and method
US10/190,282 2002-07-05
PCT/US2003/021017 WO2004006577A1 (en) 2002-07-05 2003-07-02 High-definition de-interlacing and frame doubling circuit and method

Publications (1)

Publication Number Publication Date
AU2003247786A1 true AU2003247786A1 (en) 2004-01-23

Family

ID=29999841

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003247786A Abandoned AU2003247786A1 (en) 2002-07-05 2003-07-02 High-definition de-interlacing and frame doubling circuit and method

Country Status (8)

Country Link
US (2) US6894726B2 (ko)
EP (1) EP1552691A4 (ko)
JP (1) JP5008826B2 (ko)
KR (1) KR100996216B1 (ko)
CN (1) CN1666515A (ko)
AU (1) AU2003247786A1 (ko)
MX (1) MXPA05000330A (ko)
WO (1) WO2004006577A1 (ko)

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US8115863B2 (en) * 2007-04-04 2012-02-14 Freescale Semiconductor, Inc. Video de-interlacer using pixel trajectory
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TWI348821B (en) * 2007-08-08 2011-09-11 Alpha Networks Inc Interface converting circuit
JP2012501611A (ja) * 2008-09-01 2012-01-19 ミツビシ エレクトリック ビジュアル ソリューションズ アメリカ， インコーポレイテッド 画像改善システム
US8284307B1 (en) * 2010-11-01 2012-10-09 Marseille Networks, Inc. Method for processing digital video fields
CN102184707A (zh) * 2011-03-25 2011-09-14 西安交通大学 彩色led显示装置实现灰度显示的存储控制方法
US10601425B2 (en) * 2018-05-30 2020-03-24 Intel Corporation Width and frequency conversion with PHY layer devices in PCI-express
US11467999B2 (en) 2018-06-29 2022-10-11 Intel Corporation Negotiating asymmetric link widths dynamically in a multi-lane link
US10846247B2 (en) 2019-03-05 2020-11-24 Intel Corporation Controlling partial link width states for multilane links
CN112188137B (zh) * 2019-07-01 2022-07-08 北京华航无线电测量研究所 基于fpga的高帧频逐行图像转换至标清pal隔行图像实现方法
US11836101B2 (en) 2019-11-27 2023-12-05 Intel Corporation Partial link width states for bidirectional multilane links

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Also Published As

Publication number Publication date
KR20050021440A (ko) 2005-03-07
KR100996216B1 (ko) 2010-11-24
US20050162549A1 (en) 2005-07-28
EP1552691A4 (en) 2010-05-05
US7468754B2 (en) 2008-12-23
US20040004672A1 (en) 2004-01-08
WO2004006577A1 (en) 2004-01-15
US6894726B2 (en) 2005-05-17
JP5008826B2 (ja) 2012-08-22
JP2005532740A (ja) 2005-10-27
EP1552691A1 (en) 2005-07-13
CN1666515A (zh) 2005-09-07
MXPA05000330A (es) 2005-03-31

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase