AU2003230145A1 - Cell with fixed output voltage for integrated circuit - Google Patents
Cell with fixed output voltage for integrated circuitInfo
- Publication number
- AU2003230145A1 AU2003230145A1 AU2003230145A AU2003230145A AU2003230145A1 AU 2003230145 A1 AU2003230145 A1 AU 2003230145A1 AU 2003230145 A AU2003230145 A AU 2003230145A AU 2003230145 A AU2003230145 A AU 2003230145A AU 2003230145 A1 AU2003230145 A1 AU 2003230145A1
- Authority
- AU
- Australia
- Prior art keywords
- cell
- output voltage
- integrated circuit
- fixed output
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000001105 regulatory effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Measurement Of Current Or Voltage (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0206227 | 2002-05-22 | ||
FR0206227A FR2840074A1 (fr) | 2002-05-22 | 2002-05-22 | Cellule de tension fixe pour circuit integre |
PCT/IB2003/002077 WO2003098244A1 (fr) | 2002-05-22 | 2003-05-15 | Cellule dotee d'une tension de sortie fixee pour circuit integre |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2003230145A1 true AU2003230145A1 (en) | 2003-12-02 |
Family
ID=29414984
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2003230145A Abandoned AU2003230145A1 (en) | 2002-05-22 | 2003-05-15 | Cell with fixed output voltage for integrated circuit |
Country Status (10)
Country | Link |
---|---|
US (2) | US7459928B2 (fr) |
EP (1) | EP1509778B1 (fr) |
JP (1) | JP2005526429A (fr) |
KR (1) | KR20050007548A (fr) |
CN (1) | CN100414314C (fr) |
AT (1) | ATE368866T1 (fr) |
AU (1) | AU2003230145A1 (fr) |
DE (1) | DE60315289T2 (fr) |
FR (1) | FR2840074A1 (fr) |
WO (1) | WO2003098244A1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102008060663A1 (de) * | 2008-12-08 | 2010-06-10 | KROHNE Meßtechnik GmbH & Co. KG | Schaltungsanordnung zur Erzeugung kurzer elektrischer Impulse |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR910002236B1 (ko) * | 1986-08-04 | 1991-04-08 | 미쓰비시 뎅기 가부시끼가이샤 | 반도체집적회로장치 |
EP0369047A1 (fr) * | 1988-11-15 | 1990-05-23 | Siemens Aktiengesellschaft | Dispositif de commutation d'une horloge sur une horloge de même fréquence mais en retard de phase |
JP3640671B2 (ja) * | 1993-12-16 | 2005-04-20 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴイ | 固定論理値を出力する手段の出力と回路の入力との間の接続を検査する装置及び方法 |
US5574853A (en) | 1994-01-03 | 1996-11-12 | Texas Instruments Incorporated | Testing integrated circuit designs on a computer simulation using modified serialized scan patterns |
US5444404A (en) * | 1994-03-03 | 1995-08-22 | Vlsi Technology, Inc. | Scan flip-flop with power saving feature |
US6014762A (en) * | 1997-06-23 | 2000-01-11 | Sun Microsystems, Inc. | Method and apparatus for scan test of SRAM for microprocessor without full scan capability |
EP0992809A1 (fr) * | 1998-09-28 | 2000-04-12 | Siemens Aktiengesellschaft | Circuit avec trajet d'analyse désactivable |
JP4579370B2 (ja) * | 2000-04-24 | 2010-11-10 | ルネサスエレクトロニクス株式会社 | スキャンフリップフロップ回路及びこれを用いたスキャンテスト方法 |
DE60112616T2 (de) * | 2000-10-02 | 2006-06-22 | Koninklijke Philips Electronics N.V. | Scan-test-system und methode zum manipulieren der logikwerte, die während normalbetrieb konstant bleiben |
-
2002
- 2002-05-22 FR FR0206227A patent/FR2840074A1/fr not_active Withdrawn
-
2003
- 2003-05-15 DE DE60315289T patent/DE60315289T2/de not_active Expired - Lifetime
- 2003-05-15 AT AT03722988T patent/ATE368866T1/de not_active IP Right Cessation
- 2003-05-15 CN CNB03811514XA patent/CN100414314C/zh not_active Expired - Fee Related
- 2003-05-15 EP EP03722988A patent/EP1509778B1/fr not_active Expired - Lifetime
- 2003-05-15 WO PCT/IB2003/002077 patent/WO2003098244A1/fr active IP Right Grant
- 2003-05-15 US US10/514,902 patent/US7459928B2/en active Active
- 2003-05-15 AU AU2003230145A patent/AU2003230145A1/en not_active Abandoned
- 2003-05-15 KR KR10-2004-7018553A patent/KR20050007548A/ko not_active Application Discontinuation
- 2003-05-15 JP JP2004505713A patent/JP2005526429A/ja active Pending
-
2008
- 2008-10-31 US US12/262,912 patent/US7688103B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE60315289T2 (de) | 2008-05-08 |
ATE368866T1 (de) | 2007-08-15 |
WO2003098244A1 (fr) | 2003-11-27 |
EP1509778B1 (fr) | 2007-08-01 |
CN1656385A (zh) | 2005-08-17 |
US20050180196A1 (en) | 2005-08-18 |
JP2005526429A (ja) | 2005-09-02 |
DE60315289D1 (de) | 2007-09-13 |
US7688103B2 (en) | 2010-03-30 |
US20090051385A1 (en) | 2009-02-26 |
CN100414314C (zh) | 2008-08-27 |
FR2840074A1 (fr) | 2003-11-28 |
EP1509778A1 (fr) | 2005-03-02 |
US7459928B2 (en) | 2008-12-02 |
KR20050007548A (ko) | 2005-01-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK6 | Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase |