AU2001243392A1 - An integrated circuit architecture with standard blocks - Google Patents

An integrated circuit architecture with standard blocks

Info

Publication number
AU2001243392A1
AU2001243392A1 AU2001243392A AU4339201A AU2001243392A1 AU 2001243392 A1 AU2001243392 A1 AU 2001243392A1 AU 2001243392 A AU2001243392 A AU 2001243392A AU 4339201 A AU4339201 A AU 4339201A AU 2001243392 A1 AU2001243392 A1 AU 2001243392A1
Authority
AU
Australia
Prior art keywords
integrated circuit
circuit architecture
standard blocks
blocks
standard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001243392A
Other languages
English (en)
Inventor
Jacob Avidan
Stan Chow
Dimitris Fotakis
Athanassios Katsioulas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ammocore Tech Inc
Original Assignee
Ammocore Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ammocore Tech Inc filed Critical Ammocore Tech Inc
Publication of AU2001243392A1 publication Critical patent/AU2001243392A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118Masterslice integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
AU2001243392A 2000-03-21 2001-03-02 An integrated circuit architecture with standard blocks Abandoned AU2001243392A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09532330 2000-03-21
US09/532,330 US6467074B1 (en) 2000-03-21 2000-03-21 Integrated circuit architecture with standard blocks
PCT/US2001/006807 WO2001071808A1 (fr) 2000-03-21 2001-03-02 Architecture de circuit integre pourvue de blocs normalises

Publications (1)

Publication Number Publication Date
AU2001243392A1 true AU2001243392A1 (en) 2001-10-03

Family

ID=24121332

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001243392A Abandoned AU2001243392A1 (en) 2000-03-21 2001-03-02 An integrated circuit architecture with standard blocks

Country Status (5)

Country Link
US (1) US6467074B1 (fr)
EP (1) EP1269541A1 (fr)
JP (1) JP2003528468A (fr)
AU (1) AU2001243392A1 (fr)
WO (1) WO2001071808A1 (fr)

Families Citing this family (90)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6567290B2 (en) * 2000-07-05 2003-05-20 Mosaic Systems, Inc. High-speed low-power semiconductor memory architecture
US6857116B1 (en) 2000-11-15 2005-02-15 Reshape, Inc. Optimization of abutted-pin hierarchical physical design
US6763512B2 (en) * 2001-04-06 2004-07-13 Sun Microsystems, Inc. Detailed method for routing connections using tile expansion techniques and associated methods for designing and manufacturing VLSI circuits
US6910199B2 (en) * 2001-04-23 2005-06-21 Telairity Semiconductor, Inc. Circuit group design methodologies
US6839882B2 (en) * 2001-06-01 2005-01-04 Virtual Silicon Technology, Inc. Method and apparatus for design of integrated circuits
US6892373B2 (en) * 2001-06-15 2005-05-10 Science & Technology Corporation At Unm Integrated circuit cell library
US6993731B2 (en) * 2001-06-15 2006-01-31 Science & Technology Corporation @ Unm Optimization of digital designs
WO2002103757A2 (fr) * 2001-06-15 2002-12-27 Science And Technology Corporation @ Unm Circuits numeriques a operateurs de selection
US6622294B2 (en) * 2001-09-28 2003-09-16 Intel Corporation Adaptive power routing and shield sharing to reduce shield count
DE10151379C1 (de) * 2001-10-18 2003-04-24 Infineon Technologies Ag Verfahren zur Herstellung einer integrierten Halbleiterschaltung
US6609240B2 (en) * 2001-10-31 2003-08-19 Oki Electric Industry Co., Ltd. Method of designing conductive pattern layout of LSI
US6594805B1 (en) * 2001-11-13 2003-07-15 Lsi Logic Corporation Integrated design system and method for reducing and avoiding crosstalk
US6832362B2 (en) * 2002-06-05 2004-12-14 Agilent Technologies, Inc. Process and system for repeater insertion in an IC design
US6873185B2 (en) 2002-06-19 2005-03-29 Viasic, Inc. Logic array devices having complex macro-cell architecture and methods facilitating use of same
US7392495B1 (en) * 2002-08-13 2008-06-24 Cypress Semiconductor Corporation Method and system for providing hybrid clock distribution
JP3790202B2 (ja) * 2002-09-24 2006-06-28 松下電器産業株式会社 半導体集積回路の電源配線方法および半導体集積回路
JP4837870B2 (ja) * 2002-11-05 2011-12-14 株式会社リコー 半導体集積回路のレイアウト設計方法
AU2002357880A1 (en) * 2002-12-17 2004-07-29 International Business Machines Corporation Asic clock floor planning method and structure
JP2004221231A (ja) * 2003-01-14 2004-08-05 Nec Electronics Corp レイアウトパターン生成のための装置と方法、及びそれを用いた半導体装置の製造方法
US6938226B2 (en) * 2003-01-17 2005-08-30 Infineon Technologies Ag 7-tracks standard cell library
US7010641B2 (en) * 2003-01-31 2006-03-07 Agilent Technologies, Inc. Integrated circuit routing resource optimization algorithm for random port ordering
US7146303B2 (en) * 2003-02-28 2006-12-05 Sun Microsystems, Inc. Technique for incorporating power information in register transfer logic design
US7155693B1 (en) * 2003-04-23 2006-12-26 Magma Design Automation, Inc. Floorplanning a hierarchical physical design to improve placement and routing
US20060044016A1 (en) * 2004-08-24 2006-03-02 Gasper Martin J Jr Integrated circuit with signal skew adjusting cell selected from cell library
US7107551B1 (en) * 2003-05-30 2006-09-12 Prolific, Inc. Optimization of circuit designs using a continuous spectrum of library cells
US7272803B1 (en) * 2003-06-01 2007-09-18 Cadence Design Systems, Inc. Methods and apparatus for defining manhattan power grid structures having a reduced number of vias
US7003748B1 (en) * 2003-06-01 2006-02-21 Cadence Design Systems, Inc. Methods and apparatus for defining Manhattan power grid structures beneficial to diagonal signal wiring
US7243312B1 (en) * 2003-10-24 2007-07-10 Xilinx, Inc. Method and apparatus for power optimization during an integrated circuit design process
US20050114818A1 (en) * 2003-11-21 2005-05-26 Lsi Logic Corporation Chip design command processor
US7269803B2 (en) * 2003-12-18 2007-09-11 Lsi Corporation System and method for mapping logical components to physical locations in an integrated circuit design environment
NL1025513C2 (nl) * 2004-02-18 2005-08-19 Nexus Technology B V Behuizing voor computerhardware en werkwijze voor het koelen van een dergelijke behuizing.
US7335966B2 (en) * 2004-02-26 2008-02-26 Triad Semiconductor, Inc. Configurable integrated circuit capacitor array using via mask layers
US7120892B1 (en) * 2004-03-03 2006-10-10 Xilinx, Inc. Process for adjusting data structures of a floorplan upon changes occurring
US20050210428A1 (en) * 2004-03-18 2005-09-22 Keller S B System and method for flattening hierarchical designs in VLSI circuit analysis tools
US7620743B2 (en) 2004-04-01 2009-11-17 Lsi Corporation System and method for implementing multiple instantiated configurable peripherals in a circuit design
WO2005098954A1 (fr) * 2004-04-02 2005-10-20 Triad Semiconductor, Inc. Architecture configurable avec des trous d'interconnexion pour personnaliser des circuits analogiques dans un dispositif a semi-conducteurs
US7353488B1 (en) 2004-05-27 2008-04-01 Magma Design Automation, Inc. Flow definition language for designing integrated circuit implementation flows
US20060080632A1 (en) * 2004-09-30 2006-04-13 Mathstar, Inc. Integrated circuit layout having rectilinear structure of objects
US20070277139A1 (en) * 2004-10-13 2007-11-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor Integrated Circuit and Designing Method of the Same, and Electronic Apparatus Using the Same
US7334209B1 (en) * 2004-10-15 2008-02-19 Xilinx, Inc. Method and system for generating multiple implementation views of an IC design
US7284227B1 (en) 2004-10-15 2007-10-16 Xilinx, Inc. Method and system for generating implementation files from a high level specification
US7334208B1 (en) 2004-11-09 2008-02-19 Viasic, Inc. Customization of structured ASIC devices using pre-process extraction of routing information
US20070247189A1 (en) * 2005-01-25 2007-10-25 Mathstar Field programmable semiconductor object array integrated circuit
US7788625B1 (en) * 2005-04-14 2010-08-31 Xilinx, Inc. Method and apparatus for precharacterizing systems for use in system level design of integrated circuits
US7398482B2 (en) * 2005-07-28 2008-07-08 International Business Machines Corporation Modular design method and apparatus
US7467367B1 (en) * 2005-10-27 2008-12-16 Cadence Design Systems, Inc. Method and system for clock tree synthesis of an integrated circuit
US7761831B2 (en) * 2005-12-29 2010-07-20 Mosaid Technologies Incorporated ASIC design using clock and power grid standard cell
US20080109778A1 (en) * 2006-10-23 2008-05-08 Inventec Corporation Setting method of line pitch/line width layout for logic circuit
US7577933B1 (en) * 2006-11-17 2009-08-18 Sun Microsystems, Inc. Timing driven pin assignment
US7877720B2 (en) 2007-01-08 2011-01-25 International Business Machines Corporation Method and tool for designing electronic circuits on a printed circuit board
JP2008204349A (ja) * 2007-02-22 2008-09-04 Fujitsu Ltd レイアウト設計プログラム、該プログラムを記録した記録媒体、レイアウト設計方法、およびレイアウト設計装置
US7692309B2 (en) * 2007-09-06 2010-04-06 Viasic, Inc. Configuring structured ASIC fabric using two non-adjacent via layers
US20090144595A1 (en) * 2007-11-30 2009-06-04 Mathstar, Inc. Built-in self-testing (bist) of field programmable object arrays
CN101499470B (zh) * 2008-02-01 2011-01-26 瑞昱半导体股份有限公司 集成电路电源布局及其设计方法
US7696782B2 (en) * 2008-02-15 2010-04-13 Broadcom Corporation Programmable core for implementing logic change
US7836422B1 (en) * 2008-05-15 2010-11-16 Oracle America, Inc. System, method and apparatus for optimizing multiple wire pitches in integrated circuit design
US8099702B2 (en) * 2008-07-30 2012-01-17 Synopsys, Inc. Method and apparatus for proximate placement of sequential cells
TWI369620B (en) * 2008-07-30 2012-08-01 Faraday Tech Corp Method and technique for analogue circuit synthesis
US8510700B2 (en) * 2009-02-24 2013-08-13 Syphermedia International, Inc. Method and apparatus for camouflaging a standard cell based integrated circuit with micro circuits and post processing
US10691860B2 (en) 2009-02-24 2020-06-23 Rambus Inc. Secure logic locking and configuration with camouflaged programmable micro netlists
US8418091B2 (en) 2009-02-24 2013-04-09 Syphermedia International, Inc. Method and apparatus for camouflaging a standard cell based integrated circuit
US9735781B2 (en) 2009-02-24 2017-08-15 Syphermedia International, Inc. Physically unclonable camouflage structure and methods for fabricating same
US8151235B2 (en) * 2009-02-24 2012-04-03 Syphermedia International, Inc. Camouflaging a standard cell based integrated circuit
US8225262B1 (en) * 2009-03-18 2012-07-17 Xilinx, Inc. Method of and system for placing clock circuits in an integrated circuit
US8111089B2 (en) * 2009-05-28 2012-02-07 Syphermedia International, Inc. Building block for a secure CMOS logic cell library
US8255847B1 (en) * 2009-10-01 2012-08-28 Altera Corporation Method and apparatus for automatic hierarchical design partitioning
US8402418B2 (en) * 2009-12-31 2013-03-19 Nvidia Corporation System and process for automatic clock routing in an application specific integrated circuit
US8316342B1 (en) * 2010-06-02 2012-11-20 Cadence Design Systems, Inc. Method and apparatus for concurrent design of modules across different design entry tools targeted to a single layout
US8521483B1 (en) 2010-06-02 2013-08-27 Cadence Design Systems, Inc. Method and apparatus for concurrent design of modules across different design entry tools targeted to single simulation
US8196086B2 (en) * 2010-07-21 2012-06-05 Lsi Corporation Granular channel width for power optimization
US8645893B1 (en) * 2012-10-23 2014-02-04 Arm Limited Method of generating a layout of an integrated circuit comprising both standard cells and at least one memory instance
US9032358B2 (en) 2013-03-06 2015-05-12 Qualcomm Incorporated Integrated circuit floorplan for compact clock distribution
US9761521B1 (en) 2014-10-21 2017-09-12 Macom Connectivity Solutions, Llc Flexible and robust power grid connectivity
US10097182B2 (en) 2014-12-31 2018-10-09 Stmicroelectronics, Inc. Integrated circuit layout wiring for multi-core chips
US10102327B2 (en) 2014-12-31 2018-10-16 Stmicroelectronics, Inc. Integrated circuit layout wiring for multi-core chips
MX2017009112A (es) 2015-01-14 2018-06-15 Respira Therapeutics Inc Metodos y dispositivos de dispersion de polvo.
US9436791B1 (en) * 2015-03-24 2016-09-06 International Business Machines Corporation Optimizing placement of circuit resources using a globally accessible placement memory
US20170169155A1 (en) * 2015-12-10 2017-06-15 GlobalFoundries, Inc. Method to adjust alley gap between large blocks for floorplan optimization
US9886544B2 (en) 2016-02-23 2018-02-06 Taiwan Semiconductor Manufacturing Co., Ltd. Layout checking system and method
US9640522B1 (en) 2016-04-19 2017-05-02 Qualcomm Incorporated V1 and higher layers programmable ECO standard cells
US10248753B2 (en) 2016-10-07 2019-04-02 International Business Machines Corporation Pessimism reduction in hierarchical blockage aggressors using estimated resistor and capacitor values
US10741539B2 (en) * 2017-08-30 2020-08-11 Taiwan Semiconductor Manufacturing Co., Ltd. Standard cells and variations thereof within a standard cell library
US10878163B2 (en) 2017-08-30 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including PG-aligned cells and method of generating layout of same
DE102017127276A1 (de) 2017-08-30 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Standardzellen und abwandlungen davon innerhalb einer standardzellenbibliothek
US10923596B2 (en) 2019-03-08 2021-02-16 Rambus Inc. Camouflaged FinFET and method for producing same
US11392747B2 (en) * 2019-10-30 2022-07-19 Taiwan Semiconductor Manufacturing Company Ltd. Layout method of a semiconductor device and associated system
US11328110B2 (en) 2020-04-02 2022-05-10 International Business Machines Corporation Integrated circuit including logic circuitry
US11663389B2 (en) * 2021-04-16 2023-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit layout
US11775730B2 (en) 2021-08-16 2023-10-03 International Business Machines Corporation Hierarchical large block synthesis (HLBS) filling
US20230207552A1 (en) * 2021-12-24 2023-06-29 Intel Corporation Transition cells between design blocks on a wafer

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0793358B2 (ja) 1986-11-10 1995-10-09 日本電気株式会社 ブロック配置処理方式
JPS63308343A (ja) 1987-06-10 1988-12-15 Matsushita Electric Ind Co Ltd 半導体集積回路
US5206815A (en) 1989-01-13 1993-04-27 Vlsi Technology, Inc. Method for arranging modules in an integrated circuit
US5459673A (en) 1990-10-29 1995-10-17 Ross Technology, Inc. Method and apparatus for optimizing electronic circuits
JP2509755B2 (ja) 1990-11-22 1996-06-26 株式会社東芝 半導体集積回路製造方法
JP2839722B2 (ja) 1990-12-27 1998-12-16 シャープ株式会社 集積回路装置
US5471398A (en) 1991-07-01 1995-11-28 Texas Instruments Incorporated MTOL software tool for converting an RTL behavioral model into layout information comprising bounding boxes and an associated interconnect netlist
JP2898493B2 (ja) 1992-11-26 1999-06-02 三菱電機株式会社 ミリ波またはマイクロ波icのレイアウト設計方法及びレイアウト設計装置
US5581475A (en) 1993-08-13 1996-12-03 Harris Corporation Method for interactively tailoring topography of integrated circuit layout in accordance with electromigration model-based minimum width metal and contact/via rules
US5671397A (en) 1993-12-27 1997-09-23 At&T Global Information Solutions Company Sea-of-cells array of transistors
US5495419A (en) 1994-04-19 1996-02-27 Lsi Logic Corporation Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing
US5636129A (en) 1994-04-20 1997-06-03 Her; One-Hsiow A. Electrical routing through fixed sized module and variable sized channel grids
US5638288A (en) 1994-08-24 1997-06-10 Lsi Logic Corporation Separable cells having wiring channels for routing signals between surrounding cells
JPH08258993A (ja) 1995-03-29 1996-10-08 Nippon Steel Corp 移動層充填物排出機構
US5696693A (en) * 1995-03-31 1997-12-09 Unisys Corporation Method for placing logic functions and cells in a logic design using floor planning by analogy
US5723883A (en) 1995-11-14 1998-03-03 In-Chip Gate array cell architecture and routing scheme
US5757656A (en) 1995-12-20 1998-05-26 Mentor Graphics Method for routing breakouts
US5847969A (en) 1996-05-01 1998-12-08 Hewlett-Packard Co. Integrated circuit design system and method for generating a regular structure embedded in a standard cell control block
US5892688A (en) 1996-06-28 1999-04-06 Lsi Logic Corporation Advanced modular cell placement system with iterative one dimensional preplacement optimization
US6067409A (en) * 1996-06-28 2000-05-23 Lsi Logic Corporation Advanced modular cell placement system
US5872718A (en) 1996-06-28 1999-02-16 Lsi Logic Corporation Advanced modular cell placement system
US5923060A (en) 1996-09-27 1999-07-13 In-Chip Systems, Inc. Reduced area gate array cell design based on shifted placement of alternate rows of cells
JP3469006B2 (ja) * 1996-09-30 2003-11-25 株式会社東芝 半導体集積回路及びその設計方法
US5987086A (en) 1996-11-01 1999-11-16 Motorola Inc. Automatic layout standard cell routing
US5984510A (en) 1996-11-01 1999-11-16 Motorola Inc. Automatic synthesis of standard cell layouts
US6006024A (en) * 1996-11-01 1999-12-21 Motorola, Inc. Method of routing an integrated circuit
JP2954894B2 (ja) 1996-12-13 1999-09-27 株式会社半導体理工学研究センター 集積回路設計方法、集積回路設計のためのデータベース装置および集積回路設計支援装置
US5898597A (en) * 1997-02-11 1999-04-27 Lsi Logic Corporation Integrated circuit floor plan optimization system
IT1290505B1 (it) 1997-03-28 1998-12-04 Sgs Thomson Microelectronics Procedimento di assemblaggio di moduli per realizzare un circuito integrato complesso e relativa architettura di moduli
US6110221A (en) 1997-06-23 2000-08-29 Sun Microsystems, Inc. Repeater blocks adjacent clusters of circuits
US6230304B1 (en) 1997-12-24 2001-05-08 Magma Design Automation, Inc. Method of designing a constraint-driven integrated circuit layout
US6223329B1 (en) * 1998-06-17 2001-04-24 Prosper Design Systems Pte. Ltd. Hybrid design method and apparatus for computer-aided circuit design
US6298468B1 (en) * 1999-05-04 2001-10-02 Prosper Design Systems Pte. Ltd. Placement-based pin optimization method and apparatus for computer-aided circuit design
US6308309B1 (en) 1999-08-13 2001-10-23 Xilinx, Inc. Place-holding library elements for defining routing paths

Also Published As

Publication number Publication date
JP2003528468A (ja) 2003-09-24
WO2001071808A1 (fr) 2001-09-27
EP1269541A1 (fr) 2003-01-02
US6467074B1 (en) 2002-10-15

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