US7089173B1
(en)
*
|
2000-04-26 |
2006-08-08 |
Altera Corporation |
Hardware opencore evaluation
|
US7225423B2
(en)
*
|
2000-06-30 |
2007-05-29 |
Zenasis Technologies, Inc. |
Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks
|
US8176296B2
(en)
|
2000-10-26 |
2012-05-08 |
Cypress Semiconductor Corporation |
Programmable microcontroller architecture
|
US8149048B1
(en)
|
2000-10-26 |
2012-04-03 |
Cypress Semiconductor Corporation |
Apparatus and method for programmable power management in a programmable analog circuit block
|
US7765095B1
(en)
|
2000-10-26 |
2010-07-27 |
Cypress Semiconductor Corporation |
Conditional branching in an in-circuit emulation system
|
US8160864B1
(en)
|
2000-10-26 |
2012-04-17 |
Cypress Semiconductor Corporation |
In-circuit emulator and pod synchronized boot
|
US8103496B1
(en)
|
2000-10-26 |
2012-01-24 |
Cypress Semicondutor Corporation |
Breakpoint control in an in-circuit emulation system
|
US6724220B1
(en)
|
2000-10-26 |
2004-04-20 |
Cyress Semiconductor Corporation |
Programmable microcontroller architecture (mixed analog/digital)
|
US7103863B2
(en)
*
|
2001-06-08 |
2006-09-05 |
Magma Design Automation, Inc. |
Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system
|
US6985843B2
(en)
*
|
2001-06-11 |
2006-01-10 |
Nec Electronics America, Inc. |
Cell modeling in the design of an integrated circuit
|
US6829750B2
(en)
*
|
2001-06-15 |
2004-12-07 |
Science & Technology Corporation @ Unm |
Pass-transistor very large scale integration
|
US6757882B2
(en)
*
|
2001-06-16 |
2004-06-29 |
Michael Y. Chen |
Self-describing IP package for enhanced platform based SOC design
|
US6823499B1
(en)
*
|
2001-09-18 |
2004-11-23 |
Lsi Logic Corporation |
Method for designing application specific integrated circuit structure
|
US7406674B1
(en)
|
2001-10-24 |
2008-07-29 |
Cypress Semiconductor Corporation |
Method and apparatus for generating microcontroller configuration information
|
US6751783B1
(en)
*
|
2001-10-30 |
2004-06-15 |
Lsi Logic Corporation |
System and method for optimizing an integrated circuit design
|
US8078970B1
(en)
|
2001-11-09 |
2011-12-13 |
Cypress Semiconductor Corporation |
Graphical user interface with user-selectable list-box
|
US8042093B1
(en)
|
2001-11-15 |
2011-10-18 |
Cypress Semiconductor Corporation |
System providing automatic source code generation for personalization and parameterization of user modules
|
US7844437B1
(en)
*
|
2001-11-19 |
2010-11-30 |
Cypress Semiconductor Corporation |
System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit
|
US6971004B1
(en)
|
2001-11-19 |
2005-11-29 |
Cypress Semiconductor Corp. |
System and method of dynamically reconfiguring a programmable integrated circuit
|
US8069405B1
(en)
|
2001-11-19 |
2011-11-29 |
Cypress Semiconductor Corporation |
User interface for efficiently browsing an electronic document using data-driven tabs
|
US7774190B1
(en)
|
2001-11-19 |
2010-08-10 |
Cypress Semiconductor Corporation |
Sleep and stall in an in-circuit emulation system
|
US7770113B1
(en)
|
2001-11-19 |
2010-08-03 |
Cypress Semiconductor Corporation |
System and method for dynamically generating a configuration datasheet
|
DE10159699A1
(en)
*
|
2001-12-05 |
2003-06-26 |
Infineon Technologies Ag |
Method of manufacturing a semiconductor integrated circuit
|
US8103497B1
(en)
|
2002-03-28 |
2012-01-24 |
Cypress Semiconductor Corporation |
External interface for event architecture
|
US20030208738A1
(en)
*
|
2002-04-24 |
2003-11-06 |
Yu-Ming Hsu |
Design method for full chip element on memory
|
US7308608B1
(en)
|
2002-05-01 |
2007-12-11 |
Cypress Semiconductor Corporation |
Reconfigurable testing system and method
|
US7149991B2
(en)
*
|
2002-05-30 |
2006-12-12 |
Nec Electronics America, Inc. |
Calibrating a wire load model for an integrated circuit
|
US7761845B1
(en)
|
2002-09-09 |
2010-07-20 |
Cypress Semiconductor Corporation |
Method for parameterizing a user module
|
US6804811B2
(en)
*
|
2002-09-25 |
2004-10-12 |
Lsi Logic Corporation |
Process for layout of memory matrices in integrated circuits
|
US7039887B2
(en)
*
|
2002-10-15 |
2006-05-02 |
Cadence Design Systems, Inc. |
Method and apparatus for enhancing the performance of event driven dynamic simulation of digital circuits based on netlist partitioning techniques
|
WO2004061724A1
(en)
*
|
2002-12-17 |
2004-07-22 |
International Business Machines Corporation |
Asic clock floor planning method and structure
|
US6862722B2
(en)
*
|
2002-12-20 |
2005-03-01 |
Taiwan Semiconductor Manufacturing Co., Ltd. |
Extendable method for revising patterned microelectronic conductor layer layouts
|
US6936898B2
(en)
*
|
2002-12-31 |
2005-08-30 |
Transmeta Corporation |
Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions
|
US6907588B2
(en)
*
|
2002-12-31 |
2005-06-14 |
Lsi Logic Corporation |
Congestion estimation for register transfer level code
|
WO2004068373A1
(en)
*
|
2003-01-27 |
2004-08-12 |
Koninklijke Philips Electronics N.V. |
Method of generating a floorplan for an integrated circuit
|
US7146303B2
(en)
*
|
2003-02-28 |
2006-12-05 |
Sun Microsystems, Inc. |
Technique for incorporating power information in register transfer logic design
|
US7770144B2
(en)
*
|
2003-05-28 |
2010-08-03 |
Eric Dellinger |
Modular array defined by standard cell logic
|
US6998719B2
(en)
*
|
2003-07-30 |
2006-02-14 |
Telairity Semiconductor, Inc. |
Power grid layout techniques on integrated circuits
|
US7174528B1
(en)
|
2003-10-10 |
2007-02-06 |
Transmeta Corporation |
Method and apparatus for optimizing body bias connections in CMOS circuits using a deep n-well grid structure
|
US7111269B2
(en)
*
|
2003-10-23 |
2006-09-19 |
Lsi Logic Corporation |
Comparison of two hierarchical netlist to generate change orders for updating an integrated circuit layout
|
US20050114818A1
(en)
*
|
2003-11-21 |
2005-05-26 |
Lsi Logic Corporation |
Chip design command processor
|
US7269803B2
(en)
*
|
2003-12-18 |
2007-09-11 |
Lsi Corporation |
System and method for mapping logical components to physical locations in an integrated circuit design environment
|
US7645673B1
(en)
*
|
2004-02-03 |
2010-01-12 |
Michael Pelham |
Method for generating a deep N-well pattern for an integrated circuit design
|
US7295049B1
(en)
|
2004-03-25 |
2007-11-13 |
Cypress Semiconductor Corporation |
Method and circuit for rapid alignment of signals
|
US7388260B1
(en)
|
2004-03-31 |
2008-06-17 |
Transmeta Corporation |
Structure for spanning gap in body-bias voltage routing structure
|
US7620743B2
(en)
*
|
2004-04-01 |
2009-11-17 |
Lsi Corporation |
System and method for implementing multiple instantiated configurable peripherals in a circuit design
|
US20050229143A1
(en)
*
|
2004-04-01 |
2005-10-13 |
Lsi Logic Corporation |
System and method for implementing multiple instantiated configurable peripherals in a circuit design
|
US7210113B2
(en)
*
|
2004-04-23 |
2007-04-24 |
Lsi Logic Corporation |
Process and apparatus for placing cells in an IC floorplan
|
US8286125B2
(en)
|
2004-08-13 |
2012-10-09 |
Cypress Semiconductor Corporation |
Model for a hardware device-independent method of defining embedded firmware for programmable systems
|
US8069436B2
(en)
|
2004-08-13 |
2011-11-29 |
Cypress Semiconductor Corporation |
Providing hardware independence to automate code generation of processing device firmware
|
US8612772B1
(en)
|
2004-09-10 |
2013-12-17 |
Altera Corporation |
Security core using soft key
|
US8566616B1
(en)
|
2004-09-10 |
2013-10-22 |
Altera Corporation |
Method and apparatus for protecting designs in SRAM-based programmable logic devices and the like
|
US7913206B1
(en)
|
2004-09-16 |
2011-03-22 |
Cadence Design Systems, Inc. |
Method and mechanism for performing partitioning of DRC operations
|
US7185294B2
(en)
*
|
2004-09-23 |
2007-02-27 |
Verisilicon Holdings, Co Ltd |
Standard cell library having globally scalable transistor channel length
|
US20060080632A1
(en)
*
|
2004-09-30 |
2006-04-13 |
Mathstar, Inc. |
Integrated circuit layout having rectilinear structure of objects
|
US7231626B2
(en)
*
|
2004-12-17 |
2007-06-12 |
Lsi Corporation |
Method of implementing an engineering change order in an integrated circuit design by windows
|
US20070247189A1
(en)
*
|
2005-01-25 |
2007-10-25 |
Mathstar |
Field programmable semiconductor object array integrated circuit
|
US7325214B2
(en)
*
|
2005-02-03 |
2008-01-29 |
United Microelectronics Corp. |
Method for realizing circuit layout using cell library
|
US7332976B1
(en)
|
2005-02-04 |
2008-02-19 |
Cypress Semiconductor Corporation |
Poly-phase frequency synthesis oscillator
|
US20060225015A1
(en)
*
|
2005-03-31 |
2006-10-05 |
Kamil Synek |
Various methods and apparatuses for flexible hierarchy grouping
|
JP2006303108A
(en)
*
|
2005-04-19 |
2006-11-02 |
Toshiba Corp |
Semiconductor integrated circuit
|
US7400183B1
(en)
|
2005-05-05 |
2008-07-15 |
Cypress Semiconductor Corporation |
Voltage controlled oscillator delay cell and method
|
US7360178B2
(en)
*
|
2005-05-24 |
2008-04-15 |
Lsi Logic Corporation |
Mixed-signal functions using R-cells
|
US8089461B2
(en)
|
2005-06-23 |
2012-01-03 |
Cypress Semiconductor Corporation |
Touch wake for electronic devices
|
US7343581B2
(en)
*
|
2005-06-27 |
2008-03-11 |
Tela Innovations, Inc. |
Methods for creating primitive constructed standard cells
|
US7305647B1
(en)
*
|
2005-07-28 |
2007-12-04 |
Transmeta Corporation |
Using standard pattern tiles and custom pattern tiles to generate a semiconductor design layout having a deep well structure for routing body-bias voltage
|
US7398482B2
(en)
*
|
2005-07-28 |
2008-07-08 |
International Business Machines Corporation |
Modular design method and apparatus
|
US7904852B1
(en)
*
|
2005-09-12 |
2011-03-08 |
Cadence Design Systems, Inc. |
Method and system for implementing parallel processing of electronic design automation tools
|
US7409656B1
(en)
|
2005-09-12 |
2008-08-05 |
Cadence Design Systems, Inc. |
Method and system for parallelizing computing operations
|
US7614024B2
(en)
*
|
2005-10-06 |
2009-11-03 |
Broadcom Corporation |
Method to implement metal fill during integrated circuit design and layout
|
US7401313B2
(en)
*
|
2005-10-26 |
2008-07-15 |
Lsi Corporation |
Method and apparatus for controlling congestion during integrated circuit design resynthesis
|
US20070106971A1
(en)
*
|
2005-11-04 |
2007-05-10 |
Lizotech, Inc. |
Apparatus for a routing system
|
US8085067B1
(en)
|
2005-12-21 |
2011-12-27 |
Cypress Semiconductor Corporation |
Differential-to-single ended signal converter circuit and method
|
US7590968B1
(en)
|
2006-03-01 |
2009-09-15 |
Tela Innovations, Inc. |
Methods for risk-informed chip layout generation
|
US8541879B2
(en)
|
2007-12-13 |
2013-09-24 |
Tela Innovations, Inc. |
Super-self-aligned contacts and method for making the same
|
US8245180B2
(en)
|
2006-03-09 |
2012-08-14 |
Tela Innovations, Inc. |
Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
|
US8225239B2
(en)
|
2006-03-09 |
2012-07-17 |
Tela Innovations, Inc. |
Methods for defining and utilizing sub-resolution features in linear topology
|
US8658542B2
(en)
|
2006-03-09 |
2014-02-25 |
Tela Innovations, Inc. |
Coarse grid design methods and structures
|
US8448102B2
(en)
|
2006-03-09 |
2013-05-21 |
Tela Innovations, Inc. |
Optimizing layout of irregular structures in regular layout context
|
US7956421B2
(en)
|
2008-03-13 |
2011-06-07 |
Tela Innovations, Inc. |
Cross-coupled transistor layouts in restricted gate level layout architecture
|
US9563733B2
(en)
|
2009-05-06 |
2017-02-07 |
Tela Innovations, Inc. |
Cell circuit and layout with linear finfet structures
|
US7446352B2
(en)
|
2006-03-09 |
2008-11-04 |
Tela Innovations, Inc. |
Dynamic array architecture
|
US7943967B2
(en)
*
|
2006-03-09 |
2011-05-17 |
Tela Innovations, Inc. |
Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
|
US9035359B2
(en)
|
2006-03-09 |
2015-05-19 |
Tela Innovations, Inc. |
Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
|
US7932545B2
(en)
|
2006-03-09 |
2011-04-26 |
Tela Innovations, Inc. |
Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
|
US8839175B2
(en)
|
2006-03-09 |
2014-09-16 |
Tela Innovations, Inc. |
Scalable meta-data objects
|
US7763534B2
(en)
|
2007-10-26 |
2010-07-27 |
Tela Innovations, Inc. |
Methods, structures and designs for self-aligning local interconnects used in integrated circuits
|
US8653857B2
(en)
|
2006-03-09 |
2014-02-18 |
Tela Innovations, Inc. |
Circuitry and layouts for XOR and XNOR logic
|
US8225261B2
(en)
|
2006-03-09 |
2012-07-17 |
Tela Innovations, Inc. |
Methods for defining contact grid in dynamic array architecture
|
US8247846B2
(en)
|
2006-03-09 |
2012-08-21 |
Tela Innovations, Inc. |
Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
|
US9230910B2
(en)
|
2006-03-09 |
2016-01-05 |
Tela Innovations, Inc. |
Oversized contacts and vias in layout defined by linearly constrained topology
|
US9009641B2
(en)
|
2006-03-09 |
2015-04-14 |
Tela Innovations, Inc. |
Circuits with linear finfet structures
|
US7873930B2
(en)
*
|
2006-03-24 |
2011-01-18 |
Synopsys, Inc. |
Methods and systems for optimizing designs of integrated circuits
|
US8067948B2
(en)
|
2006-03-27 |
2011-11-29 |
Cypress Semiconductor Corporation |
Input/output multiplexer bus
|
US20070256044A1
(en)
*
|
2006-04-26 |
2007-11-01 |
Gary Coryer |
System and method to power route hierarchical designs that employ macro reuse
|
US8448096B1
(en)
|
2006-06-30 |
2013-05-21 |
Cadence Design Systems, Inc. |
Method and system for parallel processing of IC design layouts
|
US7586800B1
(en)
|
2006-08-08 |
2009-09-08 |
Tela Innovations, Inc. |
Memory timing apparatus and associated methods
|
US7657856B1
(en)
|
2006-09-12 |
2010-02-02 |
Cadence Design Systems, Inc. |
Method and system for parallel processing of IC design layouts
|
US8868397B2
(en)
|
2006-11-20 |
2014-10-21 |
Sonics, Inc. |
Transaction co-validation across abstraction layers
|
US7979829B2
(en)
*
|
2007-02-20 |
2011-07-12 |
Tela Innovations, Inc. |
Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods
|
US8286107B2
(en)
|
2007-02-20 |
2012-10-09 |
Tela Innovations, Inc. |
Methods and systems for process compensation technique acceleration
|
KR100827665B1
(en)
*
|
2007-02-23 |
2008-05-07 |
삼성전자주식회사 |
Semiconductor device and layout method of decoupling capacitor thereof
|
US7888705B2
(en)
|
2007-08-02 |
2011-02-15 |
Tela Innovations, Inc. |
Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
|
US8667443B2
(en)
|
2007-03-05 |
2014-03-04 |
Tela Innovations, Inc. |
Integrated circuit cell library for multiple patterning
|
US7737724B2
(en)
|
2007-04-17 |
2010-06-15 |
Cypress Semiconductor Corporation |
Universal digital block interconnection and channel routing
|
US9564902B2
(en)
|
2007-04-17 |
2017-02-07 |
Cypress Semiconductor Corporation |
Dynamically configurable and re-configurable data path
|
US8026739B2
(en)
|
2007-04-17 |
2011-09-27 |
Cypress Semiconductor Corporation |
System level interconnect with programmable switching
|
US8040266B2
(en)
|
2007-04-17 |
2011-10-18 |
Cypress Semiconductor Corporation |
Programmable sigma-delta analog-to-digital converter
|
US8130025B2
(en)
|
2007-04-17 |
2012-03-06 |
Cypress Semiconductor Corporation |
Numerical band gap
|
US8516025B2
(en)
|
2007-04-17 |
2013-08-20 |
Cypress Semiconductor Corporation |
Clock driven dynamic datapath chaining
|
US8092083B2
(en)
|
2007-04-17 |
2012-01-10 |
Cypress Semiconductor Corporation |
Temperature sensor with digital bandgap
|
US8065653B1
(en)
|
2007-04-25 |
2011-11-22 |
Cypress Semiconductor Corporation |
Configuration of programmable IC design elements
|
US9720805B1
(en)
|
2007-04-25 |
2017-08-01 |
Cypress Semiconductor Corporation |
System and method for controlling a target device
|
US8266575B1
(en)
|
2007-04-25 |
2012-09-11 |
Cypress Semiconductor Corporation |
Systems and methods for dynamically reconfiguring a programmable system on a chip
|
US7685540B1
(en)
*
|
2007-05-03 |
2010-03-23 |
The Research Foundation Of The State University Of New York |
Standard block design: an effective approach for large scale floorplanning
|
US8049569B1
(en)
|
2007-09-05 |
2011-11-01 |
Cypress Semiconductor Corporation |
Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes
|
US20090144595A1
(en)
*
|
2007-11-30 |
2009-06-04 |
Mathstar, Inc. |
Built-in self-testing (bist) of field programmable object arrays
|
US8255845B2
(en)
*
|
2007-11-30 |
2012-08-28 |
Cadence Design Systems, Inc. |
System and method for generating flat layout
|
US8453094B2
(en)
|
2008-01-31 |
2013-05-28 |
Tela Innovations, Inc. |
Enforcement of semiconductor structure regularity for localized transistors and interconnect
|
US7939443B2
(en)
|
2008-03-27 |
2011-05-10 |
Tela Innovations, Inc. |
Methods for multi-wire routing and apparatus implementing same
|
KR20100003911A
(en)
*
|
2008-07-02 |
2010-01-12 |
삼성전자주식회사 |
Multi-chip package having three dimension mesh-based power distribution network and power distribution method thereof
|
SG10201608214SA
(en)
*
|
2008-07-16 |
2016-11-29 |
Tela Innovations Inc |
Methods for cell phasing and placement in dynamic array architecture and implementation of the same
|
US9122832B2
(en)
|
2008-08-01 |
2015-09-01 |
Tela Innovations, Inc. |
Methods for controlling microloading variation in semiconductor wafer layout and fabrication
|
US8122399B2
(en)
*
|
2008-08-28 |
2012-02-21 |
International Business Machines Corporation |
Compiler for closed-loop 1×N VLSI design
|
US8051400B2
(en)
*
|
2008-10-21 |
2011-11-01 |
Arm Limited |
Modifying integrated circuit layout
|
US8037437B2
(en)
*
|
2009-01-13 |
2011-10-11 |
Microsoft Corporation |
Optimizing systems-on-a-chip using the dynamic critical path
|
US8099701B2
(en)
*
|
2009-02-27 |
2012-01-17 |
Oracle America, Inc. |
Efficient chip routing method and apparatus for integrated circuit blocks with multiple connections
|
US20100277201A1
(en)
*
|
2009-05-01 |
2010-11-04 |
Curt Wortman |
Embedded digital ip strip chip
|
US9448964B2
(en)
|
2009-05-04 |
2016-09-20 |
Cypress Semiconductor Corporation |
Autonomous control in a programmable system
|
US8176212B1
(en)
*
|
2009-08-18 |
2012-05-08 |
Quickflex, Inc. |
Method and system for hierarchical and joinable behavior containers for reconfigurable computing
|
US8661392B2
(en)
|
2009-10-13 |
2014-02-25 |
Tela Innovations, Inc. |
Methods for cell boundary encroachment and layouts implementing the Same
|
TWI397829B
(en)
*
|
2009-11-26 |
2013-06-01 |
Mstar Semiconductor Inc |
Apparatus and method of preventing congestive placement
|
US8407647B2
(en)
*
|
2009-12-17 |
2013-03-26 |
Springsoft, Inc. |
Systems and methods for designing and making integrated circuits with consideration of wiring demand ratio
|
US20110271241A1
(en)
*
|
2010-04-29 |
2011-11-03 |
Hari Krishnamoorthy |
JOINT IMPLEMENTATION OF INTELLECTUAL PROPERTIES (IPs) IN A SYSTEM-ON-A-CHIP (SOC)
|
US8196086B2
(en)
|
2010-07-21 |
2012-06-05 |
Lsi Corporation |
Granular channel width for power optimization
|
US9159627B2
(en)
|
2010-11-12 |
2015-10-13 |
Tela Innovations, Inc. |
Methods for linewidth modification and apparatus implementing the same
|
US8316335B2
(en)
*
|
2010-12-09 |
2012-11-20 |
International Business Machines Corporation |
Multistage, hybrid synthesis processing facilitating integrated circuit layout
|
US8484589B2
(en)
*
|
2011-10-28 |
2013-07-09 |
Apple Inc. |
Logical repartitioning in design compiler
|
US8756541B2
(en)
|
2012-03-27 |
2014-06-17 |
International Business Machines Corporation |
Relative ordering circuit synthesis
|
WO2014056201A1
(en)
|
2012-10-12 |
2014-04-17 |
Mediatek Inc. |
Layout module for printed circuit board
|
US8930863B2
(en)
|
2013-03-14 |
2015-01-06 |
Atrenta, Inc. |
System and method for altering circuit design hierarchy to optimize routing and power distribution using initial RTL-level circuit description netlist
|
US9501600B2
(en)
*
|
2013-05-02 |
2016-11-22 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
Standard cells for predetermined function having different types of layout
|
US10127343B2
(en)
*
|
2014-12-11 |
2018-11-13 |
Mentor Graphics Corporation |
Circuit design layout in multiple synchronous representations
|
KR101665794B1
(en)
|
2014-12-22 |
2016-10-13 |
현대오트론 주식회사 |
Method for designing vehicle controller-only semiconductor based on die and vehicle controller-only semiconductor by the same
|
US9773772B2
(en)
|
2015-04-09 |
2017-09-26 |
Samsung Electronics Co., Ltd. |
Semiconductor device and method of fabricating the same
|
KR102321605B1
(en)
|
2015-04-09 |
2021-11-08 |
삼성전자주식회사 |
Method for designing layout of semiconductor device and method for manufacturing semiconductor device using the same
|
US10204920B2
(en)
|
2015-04-09 |
2019-02-12 |
Samsung Electronics Co., Ltd. |
Semiconductor device including polygon-shaped standard cell
|
US9690896B2
(en)
|
2015-04-09 |
2017-06-27 |
Samsung Electronics Co., Ltd. |
Method for manufacturing a semiconductor device and semiconductor device manufactured by the same
|
US9698056B2
(en)
|
2015-04-09 |
2017-07-04 |
Samsung Electronics., Ltd. |
Method for designing layout of semiconductor device and method for manufacturing semiconductor device using the same
|
US9501607B1
(en)
|
2015-06-09 |
2016-11-22 |
Globalfoundries Inc. |
Composite views for IP blocks in ASIC designs
|
US20170011139A1
(en)
*
|
2015-07-07 |
2017-01-12 |
Mentor Graphics Corporation |
Physically-aware circuit design partitioning
|
US10380292B1
(en)
*
|
2016-04-08 |
2019-08-13 |
Cadence Design Systems, Inc. |
Systems and methods for finite difference time domain simulation of an electronic design
|
US9640522B1
(en)
|
2016-04-19 |
2017-05-02 |
Qualcomm Incorporated |
V1 and higher layers programmable ECO standard cells
|
US11348000B1
(en)
|
2016-09-28 |
2022-05-31 |
Cadence Design Systems, Inc. |
System, method, and computer-program product for routing in an electronic design using deep learning
|
US11386322B1
(en)
*
|
2016-09-28 |
2022-07-12 |
Cadence Design Systems, Inc. |
System, method, and computer-program product for routing in an electronic design using deep learning
|
US10692808B2
(en)
|
2017-09-18 |
2020-06-23 |
Qualcomm Incorporated |
High performance cell design in a technology with high density metal routing
|
US11663389B2
(en)
*
|
2021-04-16 |
2023-05-30 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
Circuit layout
|