AU2001243200A1 - Method and system for wafer and device-level testing of an integrated circuit - Google Patents

Method and system for wafer and device-level testing of an integrated circuit

Info

Publication number
AU2001243200A1
AU2001243200A1 AU2001243200A AU4320001A AU2001243200A1 AU 2001243200 A1 AU2001243200 A1 AU 2001243200A1 AU 2001243200 A AU2001243200 A AU 2001243200A AU 4320001 A AU4320001 A AU 4320001A AU 2001243200 A1 AU2001243200 A1 AU 2001243200A1
Authority
AU
Australia
Prior art keywords
wafer
integrated circuit
level testing
testing
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001243200A
Other languages
English (en)
Inventor
Don Mccord
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of AU2001243200A1 publication Critical patent/AU2001243200A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318511—Wafer Test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31924—Voltage or current aspects, e.g. driver, receiver
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3016—Delay or race condition test, e.g. race hazard test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Tests Of Electronic Circuits (AREA)
AU2001243200A 2000-02-22 2001-02-21 Method and system for wafer and device-level testing of an integrated circuit Abandoned AU2001243200A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US18419200P 2000-02-22 2000-02-22
US60184192 2000-02-22
US23464700P 2000-09-22 2000-09-22
US60234647 2000-09-22
PCT/US2001/005455 WO2001063311A2 (fr) 2000-02-22 2001-02-21 Procede et systeme de test d'un circuit integre, au niveau de la tranche et des dispositifs

Publications (1)

Publication Number Publication Date
AU2001243200A1 true AU2001243200A1 (en) 2001-09-03

Family

ID=26879893

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001243200A Abandoned AU2001243200A1 (en) 2000-02-22 2001-02-21 Method and system for wafer and device-level testing of an integrated circuit

Country Status (3)

Country Link
US (1) US6801869B2 (fr)
AU (1) AU2001243200A1 (fr)
WO (1) WO2001063311A2 (fr)

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WO2001063311A2 (fr) 2000-02-22 2001-08-30 Don Mccord Procede et systeme de test d'un circuit integre, au niveau de la tranche et des dispositifs
US6927591B2 (en) 2000-09-22 2005-08-09 Mccord Don Method and system for wafer and device level testing of an integrated circuit
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US6980016B2 (en) * 2001-07-02 2005-12-27 Intel Corporation Integrated circuit burn-in systems
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US6970001B2 (en) 2003-02-20 2005-11-29 Hewlett-Packard Development Company, L.P. Variable impedance test probe
US7117405B2 (en) * 2003-04-28 2006-10-03 Kingston Technology Corp. Extender card with intercepting EEPROM for testing and programming un-programmed memory modules on a PC motherboard
US7634623B2 (en) * 2003-08-29 2009-12-15 Micron Technology, Inc. Method and apparatus for self-timed data ordering for multi-data rate memories and system incorporating same
EP1517152B1 (fr) * 2003-09-17 2008-10-29 Verigy (Singapore) Pte. Ltd. Canal avec domaines croisés d'horloge
US20050086037A1 (en) * 2003-09-29 2005-04-21 Pauley Robert S. Memory device load simulator
US20050149785A1 (en) * 2003-12-19 2005-07-07 Hassan Mohamed A. Apparatus and method for testing a flash memory unit using stress voltages
US20050138497A1 (en) * 2003-12-19 2005-06-23 Hassan Mohamed A. Apparatus and method for testing a flash memory unit
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US20050177778A1 (en) * 2004-01-23 2005-08-11 Nicholas Holian Error simulation for a memory module
US7171508B2 (en) * 2004-08-23 2007-01-30 Micron Technology, Inc. Dual port memory with asymmetric inputs and outputs, device, system and method
US7859277B2 (en) * 2006-04-24 2010-12-28 Verigy (Singapore) Pte. Ltd. Apparatus, systems and methods for processing signals between a tester and a plurality of devices under test at high temperatures and with single touchdown of a probe array
US7404122B2 (en) * 2006-05-31 2008-07-22 Agilent Technologies, Inc. Mapping logic for loading control of crossbar multiplexer select RAM
US7421632B2 (en) * 2006-05-31 2008-09-02 Verigy (Singapore) Pte. Ltd. Mapping logic for controlling loading of the select ram of an error data crossbar multiplexer
US7653504B1 (en) * 2007-01-09 2010-01-26 Xilinx, Inc. Method and apparatus for providing shorted pin information for integrated circuit testing
US7987334B2 (en) * 2008-02-28 2011-07-26 International Business Machines Corporation Apparatus, system, and method for adjusting memory hold time
TWM338356U (en) * 2008-04-08 2008-08-11 Princeton Technology Corp Circuit testing apparatus
WO2010007472A1 (fr) * 2008-07-17 2010-01-21 Freescale Semiconductor, Inc. Dé de circuit intégré, boîtier de circuit intégré et procédé pour connecter un dé de circuit intégré à un dispositif externe
TW201028841A (en) * 2008-10-02 2010-08-01 Ibm A method, apparatus or software for use in a computerised storage system comprising one or more replaceable units for managing testing of one or more replacement units
JP5407632B2 (ja) * 2009-07-22 2014-02-05 富士通株式会社 プリント基板試験支援装置、プリント基板試験支援方法、及びプリント基板試験支援プログラム
US8233336B2 (en) * 2009-09-25 2012-07-31 Infineon Technologies Ag Memory controller comprising adjustable transmitter impedance
US8166343B2 (en) * 2009-12-01 2012-04-24 Hamilton Sundstrand Corporation Processing system hardware diagnostics
TWI450118B (zh) * 2010-11-02 2014-08-21 Global Unichip Corp 混合的電子設計系統及其可重組連接矩陣
KR20130085670A (ko) * 2012-01-20 2013-07-30 삼성전자주식회사 저온에서 집적 회로를 가열하는 방법과 상기 방법을 수행할 수 있는 장치들
US20140016259A1 (en) * 2012-07-11 2014-01-16 Kuang-Lung Shih Multi-motherboard power data communication architecture for power supplies
KR101987302B1 (ko) * 2013-05-20 2019-06-10 삼성전기주식회사 패키지 검사 장치 및 패키지 검사 방법
US9152520B2 (en) * 2013-09-26 2015-10-06 Texas Instruments Incorporated Programmable interface-based validation and debug
US9524799B2 (en) * 2014-12-30 2016-12-20 Sandisk Technologies Llc Method and apparatus to tune a toggle mode interface
CN105223489A (zh) * 2015-09-01 2016-01-06 沈阳拓荆科技有限公司 一种互锁电路测试设备及测试方法
WO2018112311A1 (fr) * 2016-12-16 2018-06-21 3M Innovative Properties Company Vérification de l'intégrité structurale de matériaux à l'aide d'une impédance de référence
KR20230038407A (ko) * 2020-07-21 2023-03-20 주식회사 아도반테스토 상이한 테스트 활동이 테스트 대상 장치 리소스의 서브세트를 활용하는, 하나 이상의 테스트 대상 장비를 테스트하는 자동 테스트 장비, 프로세스 및 컴퓨터 프로그램
CN112086124B (zh) * 2020-08-31 2023-03-31 澜智集成电路(苏州)有限公司 双倍速率测试模式参数配置方法及存储介质
CN112415309B (zh) * 2020-11-04 2023-08-11 广东电网有限责任公司东莞供电局 一种母排连接器测试装置
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Also Published As

Publication number Publication date
US6801869B2 (en) 2004-10-05
US20020173926A1 (en) 2002-11-21
WO2001063311A3 (fr) 2002-03-07
WO2001063311A2 (fr) 2001-08-30

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