AU2001268872A1 - Method and apparatus for testing high performance circuits - Google Patents

Method and apparatus for testing high performance circuits

Info

Publication number
AU2001268872A1
AU2001268872A1 AU2001268872A AU6887201A AU2001268872A1 AU 2001268872 A1 AU2001268872 A1 AU 2001268872A1 AU 2001268872 A AU2001268872 A AU 2001268872A AU 6887201 A AU6887201 A AU 6887201A AU 2001268872 A1 AU2001268872 A1 AU 2001268872A1
Authority
AU
Australia
Prior art keywords
high performance
testing high
performance circuits
circuits
testing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
AU2001268872A
Inventor
Dwayne Burek
Jean-Francois Cote
Fadi Maamari
Benoit Nadeau-Dostie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LogicVision Inc
Original Assignee
LogicVision Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LogicVision Inc filed Critical LogicVision Inc
Publication of AU2001268872A1 publication Critical patent/AU2001268872A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C2029/3202—Scan chain

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
AU2001268872A 2000-06-29 2001-06-15 Method and apparatus for testing high performance circuits Withdrawn AU2001268872A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/607,128 US6510534B1 (en) 2000-06-29 2000-06-29 Method and apparatus for testing high performance circuits
US09607128 2000-06-29
PCT/CA2001/000881 WO2002001719A2 (en) 2000-06-29 2001-06-15 Method and apparatus for testing high performance circuits

Publications (1)

Publication Number Publication Date
AU2001268872A1 true AU2001268872A1 (en) 2002-01-08

Family

ID=24430938

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001268872A Withdrawn AU2001268872A1 (en) 2000-06-29 2001-06-15 Method and apparatus for testing high performance circuits

Country Status (6)

Country Link
US (1) US6510534B1 (en)
EP (1) EP1305647A2 (en)
JP (1) JP2004502147A (en)
AU (1) AU2001268872A1 (en)
CA (1) CA2410432A1 (en)
WO (1) WO2002001719A2 (en)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7356786B2 (en) * 1999-11-30 2008-04-08 Synplicity, Inc. Method and user interface for debugging an electronic system
US7065481B2 (en) * 1999-11-30 2006-06-20 Synplicity, Inc. Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer
US6931572B1 (en) * 1999-11-30 2005-08-16 Synplicity, Inc. Design instrumentation circuitry
US7072818B1 (en) * 1999-11-30 2006-07-04 Synplicity, Inc. Method and system for debugging an electronic system
US6823497B2 (en) * 1999-11-30 2004-11-23 Synplicity, Inc. Method and user interface for debugging an electronic system
US7240303B1 (en) 1999-11-30 2007-07-03 Synplicity, Inc. Hardware/software co-debugging in a hardware description language
US6581191B1 (en) * 1999-11-30 2003-06-17 Synplicity, Inc. Hardware debugging in a hardware description language
JP2001255356A (en) * 2000-03-08 2001-09-21 Matsushita Electric Ind Co Ltd Test-pattern generation method and test method for semiconductor integrated circuit
US6735563B1 (en) * 2000-07-13 2004-05-11 Qualcomm, Inc. Method and apparatus for constructing voice templates for a speaker-independent voice recognition system
JP2002071758A (en) * 2000-08-29 2002-03-12 Mitsubishi Electric Corp Apparatus for testing semiconductor integrated circuit
US6665828B1 (en) * 2000-09-19 2003-12-16 International Business Machines Corporation Globally distributed scan blocks
US7222315B2 (en) * 2000-11-28 2007-05-22 Synplicity, Inc. Hardware-based HDL code coverage and design analysis
US7007213B2 (en) * 2001-02-15 2006-02-28 Syntest Technologies, Inc. Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
US8091002B2 (en) 2001-02-15 2012-01-03 Syntest Technologies, Inc. Multiple-capture DFT system to reduce peak capture power during self-test or scan test
US8769359B2 (en) 2001-02-15 2014-07-01 Syntest Technologies, Inc. Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
FR2821436B1 (en) * 2001-02-26 2004-07-23 St Microelectronics Sa METHOD AND SYSTEM FOR TESTING AN INTEGRATED CIRCUIT
US6671848B1 (en) * 2001-03-20 2003-12-30 Advanced Micro Devices, Inc. Test circuit for exposing higher order speed paths
US20020194565A1 (en) * 2001-06-18 2002-12-19 Karim Arabi Simultaneous built-in self-testing of multiple identical blocks of integrated circuitry
EP1438662A2 (en) * 2001-10-11 2004-07-21 Altera Corporation Error detection on programmable logic resources
US7644333B2 (en) * 2001-12-18 2010-01-05 Christopher John Hill Restartable logic BIST controller
US7058866B2 (en) * 2002-04-24 2006-06-06 International Business Machines Corporation Method and system for an on-chip AC self-test controller
US7827510B1 (en) 2002-06-07 2010-11-02 Synopsys, Inc. Enhanced hardware debugging with embedded FPGAS in a hardware description language
US20040153926A1 (en) * 2002-10-30 2004-08-05 Abdel-Hafez Khader S. Method and apparatus for testing asynchronous set/reset faults in a scan-based integrated circuit
US20040085082A1 (en) * 2002-10-30 2004-05-06 Townley Kent Richard High -frequency scan testability with low-speed testers
KR20060019565A (en) * 2003-06-03 2006-03-03 코닌클리즈케 필립스 일렉트로닉스 엔.브이. Delay-fault testing method, related system and circuit
US7447960B2 (en) * 2003-08-07 2008-11-04 International Business Machines Corporation Method of efficiently loading scan and non-scan memory elements
GB0330076D0 (en) * 2003-12-27 2004-02-04 Koninkl Philips Electronics Nv Delay fault test circuitry and related method
KR100594257B1 (en) * 2004-02-26 2006-06-30 삼성전자주식회사 System-on-chip having built-in self test circuits and self test method of the same
US7155651B2 (en) * 2004-04-22 2006-12-26 Logicvision, Inc. Clock controller for at-speed testing of scan circuits
US8621304B2 (en) * 2004-10-07 2013-12-31 Hewlett-Packard Development Company, L.P. Built-in self-test system and method for an integrated circuit
US8205186B1 (en) 2005-04-11 2012-06-19 Synopsys, Inc. Incremental modification of instrumentation logic
CN101258417B (en) * 2005-09-08 2011-04-13 Nxp股份有限公司 Scan testing methods
US8024631B1 (en) * 2006-11-07 2011-09-20 Marvell International Ltd. Scan testing system and method
JP2008122159A (en) * 2006-11-09 2008-05-29 Toshiba Corp Semiconductor integrated circuit
US20100269002A1 (en) * 2009-04-21 2010-10-21 Texas Instruments Incorporated Pseudo-Random Balanced Scan Burnin
US8458635B2 (en) * 2009-12-04 2013-06-04 Synopsys, Inc. Convolution computation for many-core processor architectures
US20110296259A1 (en) * 2010-05-26 2011-12-01 International Business Machines Corporation Testing memory arrays and logic with abist circuitry
US9140754B2 (en) 2011-02-28 2015-09-22 Texas Instruments Incorporated Scan-based MCM interconnecting testing
US8850280B2 (en) * 2011-10-28 2014-09-30 Lsi Corporation Scan enable timing control for testing of scan cells
US9595350B2 (en) * 2012-11-05 2017-03-14 Nxp Usa, Inc. Hardware-based memory initialization
US9182445B2 (en) * 2013-05-06 2015-11-10 Broadcom Corporation Integrated circuit with toggle suppression logic
US9588176B1 (en) * 2015-01-30 2017-03-07 Altera Corporation Techniques for using scan storage circuits
US10520547B2 (en) * 2017-09-29 2019-12-31 Silicon Laboratories Inc. Transition scan coverage for cross clock domain logic
CN109085420A (en) * 2018-09-18 2018-12-25 四川爱联科技有限公司 Voltage monitoring system and monitoring method based on NB-IoT technology
KR102681969B1 (en) * 2019-01-10 2024-07-08 삼성전자주식회사 System-on-chip for at-speed test of logic circuit and operating method thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5329533A (en) 1991-12-26 1994-07-12 At&T Bell Laboratories Partial-scan built-in self-test technique
US5349587A (en) 1992-03-26 1994-09-20 Northern Telecom Limited Multiple clock rate test apparatus for testing digital systems
US5450418A (en) * 1992-12-23 1995-09-12 Advanced Micro Devices, Inc. Pseudo master slave capture mechanism for scan elements
CA2219847C (en) * 1996-11-20 2000-10-03 Logicvision, Inc. Method and apparatus for scan testing digital circuits
US5889788A (en) * 1997-02-03 1999-03-30 Motorola, Inc. Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation
US6327684B1 (en) * 1999-05-11 2001-12-04 Logicvision, Inc. Method of testing at-speed circuits having asynchronous clocks and controller for use therewith
US6327685B1 (en) * 1999-05-12 2001-12-04 International Business Machines Corporation Logic built-in self test
US6442722B1 (en) * 1999-10-29 2002-08-27 Logicvision, Inc. Method and apparatus for testing circuits with multiple clocks

Also Published As

Publication number Publication date
US6510534B1 (en) 2003-01-21
WO2002001719A3 (en) 2002-09-19
CA2410432A1 (en) 2002-01-03
EP1305647A2 (en) 2003-05-02
JP2004502147A (en) 2004-01-22
WO2002001719A2 (en) 2002-01-03

Similar Documents

Publication Publication Date Title
AU2001268872A1 (en) Method and apparatus for testing high performance circuits
AU2001282704A1 (en) Method and apparatus for well testing
AUPR157300A0 (en) An apparatus and method (bin03)
AUPR157600A0 (en) An apparatus and method (bin04)
AUPR157400A0 (en) An apparatus and method (bin01)
EP1233275A3 (en) Circuit board testing apparatus and method
AU2001247753A1 (en) Method and apparatus for integrated-battery devices
AU1121801A (en) Method and apparatus for testing circuits with multiple clocks
AU2001261833A1 (en) Method and apparatus for multicast performance measurement
WO2002022264A8 (en) Method and apparatus for gradient generation
AU2001272733A1 (en) Apparatus and method for electrical testing of electrical circuits
AU2001293574A1 (en) System and method for testing integrated circuit devices
AU9517901A (en) Tyre testing method and apparatus
AU2001251415A1 (en) Method and apparatus for manufacturing an interconnect structure
AU2001264986A1 (en) Method and apparatus for facilitating relocation
AU2002330002A1 (en) Methods and apparatus for testing electronic circuits
AU4677301A (en) Apparatus for and method of testing applications
AU2002345613A1 (en) Method and apparatus for testing engines
SG97186A1 (en) Method and apparatus for inspecting components
AU2001259609A1 (en) Method and apparatus for sorting semiconductor devices
SG101949A1 (en) Method and apparatus for testing an integrated circuit
AU2217101A (en) Apparatus and method for shared line testing
AU2002213415A1 (en) Method and apparatus for testing for latch-up in integrated circuits
AU2002227345A1 (en) Method and apparatus for evaluating software
AU2001296194A1 (en) Capacity stress testing method and apparatus