ATE64020T1 - Verfahren und vorrichtung zum speicherzugriff in mehrprozessorsystemen. - Google Patents

Verfahren und vorrichtung zum speicherzugriff in mehrprozessorsystemen.

Info

Publication number
ATE64020T1
ATE64020T1 AT85300858T AT85300858T ATE64020T1 AT E64020 T1 ATE64020 T1 AT E64020T1 AT 85300858 T AT85300858 T AT 85300858T AT 85300858 T AT85300858 T AT 85300858T AT E64020 T1 ATE64020 T1 AT E64020T1
Authority
AT
Austria
Prior art keywords
buffer
memory access
multiprocessor systems
rmw
write
Prior art date
Application number
AT85300858T
Other languages
English (en)
Inventor
Paul K Rodman
Joseph L Ardini
David B Papworth
Original Assignee
Prime Computer Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Prime Computer Inc filed Critical Prime Computer Inc
Application granted granted Critical
Publication of ATE64020T1 publication Critical patent/ATE64020T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
AT85300858T 1984-02-10 1985-02-08 Verfahren und vorrichtung zum speicherzugriff in mehrprozessorsystemen. ATE64020T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/578,797 US4561051A (en) 1984-02-10 1984-02-10 Memory access method and apparatus in multiple processor systems
EP85300858A EP0168121B1 (de) 1984-02-10 1985-02-08 Verfahren und Vorrichtung zum Speicherzugriff in Mehrprozessorsystemen

Publications (1)

Publication Number Publication Date
ATE64020T1 true ATE64020T1 (de) 1991-06-15

Family

ID=24314358

Family Applications (1)

Application Number Title Priority Date Filing Date
AT85300858T ATE64020T1 (de) 1984-02-10 1985-02-08 Verfahren und vorrichtung zum speicherzugriff in mehrprozessorsystemen.

Country Status (6)

Country Link
US (1) US4561051A (de)
EP (1) EP0168121B1 (de)
JP (1) JPS60237567A (de)
AT (1) ATE64020T1 (de)
CA (1) CA1223973A (de)
DE (1) DE3582962D1 (de)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0760422B2 (ja) * 1983-12-30 1995-06-28 株式会社日立製作所 記憶ロツク方式
US4862350A (en) * 1984-08-03 1989-08-29 International Business Machines Corp. Architecture for a distributive microprocessing system
US4679148A (en) * 1985-05-01 1987-07-07 Ball Corporation Glass machine controller
JPS6297036A (ja) * 1985-07-31 1987-05-06 テキサス インスツルメンツ インコ−ポレイテツド 計算機システム
US5291581A (en) * 1987-07-01 1994-03-01 Digital Equipment Corporation Apparatus and method for synchronization of access to main memory signal groups in a multiprocessor data processing system
AU614044B2 (en) * 1988-03-25 1991-08-15 Nec Corporation Information processing system capable of quickly detecting an extended buffer memory regardless of a state of a main memory device
US5301278A (en) * 1988-04-29 1994-04-05 International Business Machines Corporation Flexible dynamic memory controller
US5247649A (en) * 1988-05-06 1993-09-21 Hitachi, Ltd. Multi-processor system having a multi-port cache memory
US5089952A (en) * 1988-10-07 1992-02-18 International Business Machines Corporation Method for allowing weak searchers to access pointer-connected data structures without locking
US5129072A (en) * 1989-03-08 1992-07-07 Hewlett-Packard Company System for minimizing initiator processor interrupts by protocol controller in a computer bus system
US5179679A (en) * 1989-04-07 1993-01-12 Shoemaker Kenneth D Apparatus and method for permitting reading of data from an external memory when data is stored in a write buffer in the event of a cache read miss
JP3637054B2 (ja) * 1989-09-11 2005-04-06 エルジー・エレクトロニクス・インコーポレーテッド キャッシュ/メインメモリのコンシステンシを維持するための装置及び方法
US5136714A (en) * 1989-12-04 1992-08-04 International Business Machines Corporation Method and apparatus for implementing inter-processor interrupts using shared memory storage in a multi-processor computer system
US5131085A (en) * 1989-12-04 1992-07-14 International Business Machines Corporation High performance shared main storage interface
JP2665813B2 (ja) * 1990-02-23 1997-10-22 三菱電機株式会社 記憶制御装置
US5446865A (en) * 1990-03-13 1995-08-29 At&T Corp. Processor adapted for sharing memory with more than one type of processor
US5193167A (en) * 1990-06-29 1993-03-09 Digital Equipment Corporation Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system
US5404482A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills
US5276835A (en) * 1990-12-14 1994-01-04 International Business Machines Corporation Non-blocking serialization for caching data in a shared cache
JP2586219B2 (ja) * 1990-12-20 1997-02-26 日本電気株式会社 高速媒体優先解放型排他方式
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5430860A (en) * 1991-09-17 1995-07-04 International Business Machines Inc. Mechanism for efficiently releasing memory lock, after allowing completion of current atomic sequence
US5506980A (en) * 1991-10-22 1996-04-09 Hitachi, Ltd. Method and apparatus for parallel processing of a large data array utilizing a shared auxiliary memory
JPH05210640A (ja) * 1992-01-31 1993-08-20 Hitachi Ltd マルチプロセッサシステム
EP0636256B1 (de) 1992-03-31 1997-06-04 Seiko Epson Corporation Befehlsablauffolgeplanung von einem risc-superskalarprozessor
DE69308548T2 (de) 1992-05-01 1997-06-12 Seiko Epson Corp Vorrichtung und verfahren zum befehlsabschluss in einem superskalaren prozessor.
DE69330889T2 (de) 1992-12-31 2002-03-28 Seiko Epson Corp System und Verfahren zur Änderung der Namen von Registern
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US5666515A (en) * 1993-02-18 1997-09-09 Unisys Corporation Information processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked address
US5592641A (en) * 1993-06-30 1997-01-07 Intel Corporation Method and device for selectively locking write access to blocks in a memory array using write protect inputs and block enabled status
US5566317A (en) * 1994-06-14 1996-10-15 International Business Machines Corporation Method and apparatus for computer disk drive management
US5924128A (en) * 1996-06-20 1999-07-13 International Business Machines Corporation Pseudo zero cycle address generator and fast memory access
US6078991A (en) * 1997-04-14 2000-06-20 International Business Machines Corporation Method and system for speculatively requesting system data bus for sourcing cache memory data within a multiprocessor data-processing system
US5895484A (en) * 1997-04-14 1999-04-20 International Business Machines Corporation Method and system for speculatively accessing cache memory data within a multiprocessor data-processing system using a cache controller
US6055608A (en) * 1997-04-14 2000-04-25 International Business Machines Corporation Method and system for speculatively sourcing cache memory data within a multiprocessor data-processing system
US5924118A (en) * 1997-04-14 1999-07-13 International Business Machines Corporation Method and system for speculatively sourcing cache memory data prior to upstream cache invalidation within a multiprocessor data-processing system
US6314493B1 (en) 1998-02-03 2001-11-06 International Business Machines Corporation Branch history cache
US6701429B1 (en) * 1998-12-03 2004-03-02 Telefonaktiebolaget Lm Ericsson(Publ) System and method of start-up in efficient way for multi-processor systems based on returned identification information read from pre-determined memory location
US6567094B1 (en) * 1999-09-27 2003-05-20 Xerox Corporation System for controlling read and write streams in a circular FIFO buffer
GB0114592D0 (en) * 2001-06-14 2001-08-08 Pace Micro Tech Plc Central processing unit architectures
US8219762B1 (en) 2004-08-13 2012-07-10 Oracle America, Inc. Computer system and method for leasing memory location to allow predictable access to memory location
US7412572B1 (en) 2004-03-17 2008-08-12 Sun Microsystems, Inc. Multiple-location read, single-location write operations using transient blocking synchronization support
US7418543B2 (en) * 2004-12-21 2008-08-26 Intel Corporation Processor having content addressable memory with command ordering
GB0523293D0 (en) * 2005-11-16 2005-12-21 Ibm Apparatus and method for controlling data copy services
EP2159702B1 (de) * 2007-06-20 2013-04-17 Fujitsu Limited Cache-steuereinrichtung und steuerverfahren

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3108256A (en) * 1958-12-30 1963-10-22 Ibm Logical clearing of memory devices
US3568157A (en) * 1963-12-31 1971-03-02 Bell Telephone Labor Inc Program controlled data processing system
US3435418A (en) * 1965-05-27 1969-03-25 Ibm Record retrieval and record hold system
US3469239A (en) * 1965-12-02 1969-09-23 Hughes Aircraft Co Interlocking means for a multi-processor system
US3508205A (en) * 1967-01-17 1970-04-21 Computer Usage Co Inc Communications security system
US3573736A (en) * 1968-01-15 1971-04-06 Ibm Interruption and interlock arrangement
US3528061A (en) * 1968-07-05 1970-09-08 Ibm Interlock arrangement
US3551892A (en) * 1969-01-15 1970-12-29 Ibm Interaction in a multi-processing system utilizing central timers
US3631405A (en) * 1969-11-12 1971-12-28 Honeywell Inc Sharing of microprograms between processors
DE2064383C3 (de) * 1970-01-12 1981-02-26 Fujitsu Ltd., Kawasaki, Kanagawa (Japan) Datenverarbeitungsanlage mit mehreren zentralen Verarbeitungseinrichtungen
US3725872A (en) * 1971-03-03 1973-04-03 Burroughs Corp Data processing system having status indicating and storage means
US3761883A (en) * 1972-01-20 1973-09-25 Ibm Storage protect key array for a multiprocessing system
GB1410631A (en) * 1972-01-26 1975-10-22 Plessey Co Ltd Data processing system interrupt arrangements
US3848234A (en) * 1973-04-04 1974-11-12 Sperry Rand Corp Multi-processor system with multiple cache memories
US4073005A (en) * 1974-01-21 1978-02-07 Control Data Corporation Multi-processor computer system
FR129151A (de) * 1974-02-09
GB1536853A (en) * 1975-05-01 1978-12-20 Plessey Co Ltd Data processing read and hold facility
US4000485A (en) * 1975-06-30 1976-12-28 Honeywell Information Systems, Inc. Data processing system providing locked operation of shared resources
US4162529A (en) * 1975-12-04 1979-07-24 Tokyo Shibaura Electric Co., Ltd. Interruption control system in a multiprocessing system
US4037215A (en) * 1976-04-30 1977-07-19 International Business Machines Corporation Key controlled address relocation translation system
US4038645A (en) * 1976-04-30 1977-07-26 International Business Machines Corporation Non-translatable storage protection control system
US4099243A (en) * 1977-01-18 1978-07-04 Honeywell Information Systems Inc. Memory block protection apparatus
US4157586A (en) * 1977-05-05 1979-06-05 International Business Machines Corporation Technique for performing partial stores in store-thru memory configuration
US4136386A (en) * 1977-10-06 1979-01-23 International Business Machines Corporation Backing store access coordination in a multi-processor system
JPS596415B2 (ja) * 1977-10-28 1984-02-10 株式会社日立製作所 多重情報処理システム
US4245306A (en) * 1978-12-21 1981-01-13 Burroughs Corporation Selection of addressed processor in a multi-processor network
US4345309A (en) * 1980-01-28 1982-08-17 Digital Equipment Corporation Relating to cached multiprocessor system with pipeline timing
US4394733A (en) * 1980-11-14 1983-07-19 Sperry Corporation Cache/disk subsystem

Also Published As

Publication number Publication date
US4561051A (en) 1985-12-24
JPS60237567A (ja) 1985-11-26
EP0168121B1 (de) 1991-05-29
EP0168121A1 (de) 1986-01-15
DE3582962D1 (de) 1991-07-04
CA1223973A (en) 1987-07-07

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