ATE528794T1 - Verfahren zur herstellung von lokalisierten geoi- strukturen, die durch germanium-anreicherung erhalten werden - Google Patents

Verfahren zur herstellung von lokalisierten geoi- strukturen, die durch germanium-anreicherung erhalten werden

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Publication number
ATE528794T1
ATE528794T1 AT09168024T AT09168024T ATE528794T1 AT E528794 T1 ATE528794 T1 AT E528794T1 AT 09168024 T AT09168024 T AT 09168024T AT 09168024 T AT09168024 T AT 09168024T AT E528794 T1 ATE528794 T1 AT E528794T1
Authority
AT
Austria
Prior art keywords
layer
sige
germanium
silicon
forming
Prior art date
Application number
AT09168024T
Other languages
English (en)
Inventor
Jean-Francois Damlencourt
Benjamin Vincent
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE528794T1 publication Critical patent/ATE528794T1/de

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28255Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Silicates, Zeolites, And Molecular Sieves (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Thin Film Transistor (AREA)
  • Silicon Compounds (AREA)
AT09168024T 2008-08-22 2009-08-18 Verfahren zur herstellung von lokalisierten geoi- strukturen, die durch germanium-anreicherung erhalten werden ATE528794T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0855671A FR2935194B1 (fr) 2008-08-22 2008-08-22 Procede de realisation de structures geoi localisees, obtenues par enrichissement en germanium

Publications (1)

Publication Number Publication Date
ATE528794T1 true ATE528794T1 (de) 2011-10-15

Family

ID=40451252

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09168024T ATE528794T1 (de) 2008-08-22 2009-08-18 Verfahren zur herstellung von lokalisierten geoi- strukturen, die durch germanium-anreicherung erhalten werden

Country Status (5)

Country Link
US (1) US9040391B2 (de)
EP (1) EP2157603B1 (de)
JP (1) JP2010050459A (de)
AT (1) ATE528794T1 (de)
FR (1) FR2935194B1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102184940B (zh) * 2011-03-30 2014-01-08 清华大学 半导体结构及其形成方法
JP2014187259A (ja) 2013-03-25 2014-10-02 Toshiba Corp 半導体装置の製造方法
US9406508B2 (en) * 2013-10-31 2016-08-02 Samsung Electronics Co., Ltd. Methods of forming a semiconductor layer including germanium with low defectivity
CN104733320B (zh) * 2013-12-24 2018-01-30 中芯国际集成电路制造(上海)有限公司 场效应晶体管及其制备方法
FR3030882B1 (fr) 2014-12-22 2018-03-09 Commissariat A L'energie Atomique Et Aux Energies Alternatives Circuit integre comportant des transistors pmos a tensions de seuil distinctes
US9698224B2 (en) 2015-06-19 2017-07-04 International Business Machines Corporation Silicon germanium fin formation via condensation
US10600638B2 (en) 2016-10-24 2020-03-24 International Business Machines Corporation Nanosheet transistors with sharp junctions
CN107359203A (zh) * 2017-05-12 2017-11-17 惠科股份有限公司 显示面板和显示装置
US10147820B1 (en) 2017-07-26 2018-12-04 International Business Machines Corporation Germanium condensation for replacement metal gate devices with silicon germanium channel
US10690853B2 (en) 2018-06-25 2020-06-23 International Business Machines Corporation Optoelectronics integration using semiconductor on insulator substrate
US10699967B2 (en) 2018-06-28 2020-06-30 International Business Machines Corporation Co-integration of high carrier mobility PFET and NFET devices on the same substrate using low temperature condensation
FR3088481B1 (fr) * 2018-11-14 2024-06-07 Commissariat A Lenergie Atomique Et Aux Energies Alternatives Procede de fabrication d’un transistor a effet de champ a jonction alignee avec des espaceurs

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3547419B2 (ja) * 2001-03-13 2004-07-28 株式会社東芝 半導体装置及びその製造方法
US7125458B2 (en) * 2003-09-12 2006-10-24 International Business Machines Corporation Formation of a silicon germanium-on-insulator structure by oxidation of a buried porous silicon layer
US20050221591A1 (en) * 2004-04-06 2005-10-06 International Business Machines Corporation Method of forming high-quality relaxed SiGe alloy layers on bulk Si substrates
US7141115B2 (en) * 2004-09-02 2006-11-28 International Business Machines Corporation Method of producing silicon-germanium-on-insulator material using unstrained Ge-containing source layers
EP1801854B1 (de) * 2004-09-24 2015-06-24 Shin-Etsu Handotai Co., Ltd. Verfahren zur herstellung eines halbleiter-wafers
FR2898215B1 (fr) * 2006-03-01 2008-05-16 Commissariat Energie Atomique Procede de fabrication d'un substrat par condensation germanium
FR2902234B1 (fr) 2006-06-12 2008-10-10 Commissariat Energie Atomique PROCEDE DE REALISATION DE ZONES A BASE DE Si1-yGey DE DIFFERENTES TENEURS EN Ge SUR UN MEME SUBSTRAT PAR CONDENSATION DE GERMANIUM

Also Published As

Publication number Publication date
FR2935194A1 (fr) 2010-02-26
US20100044836A1 (en) 2010-02-25
EP2157603A1 (de) 2010-02-24
JP2010050459A (ja) 2010-03-04
US9040391B2 (en) 2015-05-26
EP2157603B1 (de) 2011-10-12
FR2935194B1 (fr) 2010-10-08

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