ATE489678T1 - Nicht-blockierender adressschalter mit flachen warteschlangen pro agent - Google Patents

Nicht-blockierender adressschalter mit flachen warteschlangen pro agent

Info

Publication number
ATE489678T1
ATE489678T1 AT06801345T AT06801345T ATE489678T1 AT E489678 T1 ATE489678 T1 AT E489678T1 AT 06801345 T AT06801345 T AT 06801345T AT 06801345 T AT06801345 T AT 06801345T AT E489678 T1 ATE489678 T1 AT E489678T1
Authority
AT
Austria
Prior art keywords
storage locations
switch
flat
interconnect
address switch
Prior art date
Application number
AT06801345T
Other languages
German (de)
English (en)
Inventor
Sridhar P Subramanian
James B Keller
George Kong Yiu
Ruchi Wadhawan
Ramesh Gunna
Original Assignee
Apple Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Apple Inc filed Critical Apple Inc
Application granted granted Critical
Publication of ATE489678T1 publication Critical patent/ATE489678T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)
  • Measuring Or Testing Involving Enzymes Or Micro-Organisms (AREA)
AT06801345T 2005-08-11 2006-08-11 Nicht-blockierender adressschalter mit flachen warteschlangen pro agent ATE489678T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/201,581 US7461190B2 (en) 2005-08-11 2005-08-11 Non-blocking address switch with shallow per agent queues
PCT/US2006/031520 WO2007022018A1 (en) 2005-08-11 2006-08-11 Non-blocking address switch with shallow per agent queues

Publications (1)

Publication Number Publication Date
ATE489678T1 true ATE489678T1 (de) 2010-12-15

Family

ID=37440602

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06801345T ATE489678T1 (de) 2005-08-11 2006-08-11 Nicht-blockierender adressschalter mit flachen warteschlangen pro agent

Country Status (9)

Country Link
US (3) US7461190B2 (enExample)
EP (1) EP1922629B1 (enExample)
JP (1) JP4851523B2 (enExample)
CN (1) CN101305354B (enExample)
AT (1) ATE489678T1 (enExample)
DE (1) DE602006018483D1 (enExample)
ES (1) ES2354748T3 (enExample)
TW (1) TWI396091B (enExample)
WO (1) WO2007022018A1 (enExample)

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7062582B1 (en) 2003-03-14 2006-06-13 Marvell International Ltd. Method and apparatus for bus arbitration dynamic priority based on waiting period
US9087036B1 (en) 2004-08-12 2015-07-21 Sonics, Inc. Methods and apparatuses for time annotated transaction level modeling
US7620746B2 (en) * 2005-09-29 2009-11-17 Apple Inc. Functional DMA performing operation on DMA data and writing result of operation
US20070112945A1 (en) * 2005-11-12 2007-05-17 Lori Brown Supply and demand project management tool
US8868397B2 (en) * 2006-11-20 2014-10-21 Sonics, Inc. Transaction co-validation across abstraction layers
US8069279B2 (en) 2007-03-05 2011-11-29 Apple Inc. Data flow control within and between DMA channels
US20080270658A1 (en) * 2007-04-27 2008-10-30 Matsushita Electric Industrial Co., Ltd. Processor system, bus controlling method, and semiconductor device
US20080320255A1 (en) * 2007-06-25 2008-12-25 Sonics, Inc. Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets
US8112450B2 (en) * 2008-01-31 2012-02-07 Microsoft Corporation Priority messaging and priority scheduling
JP5147584B2 (ja) * 2008-07-23 2013-02-20 株式会社日立製作所 ストレージサブシステム及びコントローラによるコマンド実行方法
US8121129B2 (en) * 2008-12-15 2012-02-21 International Business Machines Corporation Optimizing throughput of data in a communications network
US9514074B2 (en) 2009-02-13 2016-12-06 The Regents Of The University Of Michigan Single cycle arbitration within an interconnect
US8199759B2 (en) * 2009-05-29 2012-06-12 Intel Corporation Method and apparatus for enabling ID based streams over PCI express
US8611335B1 (en) * 2009-08-13 2013-12-17 Google, Inc. System and method for assigning paths for data flows through a wide-area network
US8351594B2 (en) * 2010-02-08 2013-01-08 Genesys Telecommunications Laboratories, Inc. System for indicating priority levels for transaction and task engagement in a call center
US8379659B2 (en) * 2010-03-29 2013-02-19 Intel Corporation Performance and traffic aware heterogeneous interconnection network
US8972995B2 (en) 2010-08-06 2015-03-03 Sonics, Inc. Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads
US8868855B2 (en) * 2011-02-28 2014-10-21 Hewlett-Packard Development Company, L.P. Request management system and method for dynamically managing prioritized requests
CN102736997B (zh) * 2011-04-01 2017-05-03 中兴通讯股份有限公司 一种片上互联总线的仲裁方法和系统
US9021156B2 (en) 2011-08-31 2015-04-28 Prashanth Nimmala Integrating intellectual property (IP) blocks into a processor
US9176913B2 (en) 2011-09-07 2015-11-03 Apple Inc. Coherence switch for I/O traffic
CN103024699B (zh) * 2011-09-22 2016-05-25 北京神州泰岳软件股份有限公司 一种短信发送方法和一种信息资源站实体
US8713240B2 (en) 2011-09-29 2014-04-29 Intel Corporation Providing multiple decode options for a system-on-chip (SoC) fabric
US8711875B2 (en) 2011-09-29 2014-04-29 Intel Corporation Aggregating completion messages in a sideband interface
US8929373B2 (en) 2011-09-29 2015-01-06 Intel Corporation Sending packets with expanded headers
US8713234B2 (en) * 2011-09-29 2014-04-29 Intel Corporation Supporting multiple channels of a single interface
US8775700B2 (en) 2011-09-29 2014-07-08 Intel Corporation Issuing requests to a fabric
US8874976B2 (en) 2011-09-29 2014-10-28 Intel Corporation Providing error handling support to legacy devices
US8805926B2 (en) 2011-09-29 2014-08-12 Intel Corporation Common idle state, active state and credit management for an interface
US9053251B2 (en) 2011-11-29 2015-06-09 Intel Corporation Providing a sideband message interface for system on a chip (SoC)
US8856415B2 (en) * 2012-02-01 2014-10-07 National Instruments Corporation Bus arbitration for a real-time computer system
US8904451B2 (en) * 2012-04-13 2014-12-02 Theplatform, Llc Systems for prioritizing video processing events based on availability of media file and agent to process the event type
US8982695B2 (en) * 2012-09-29 2015-03-17 Intel Corporation Anti-starvation and bounce-reduction mechanism for a two-dimensional bufferless interconnect
US20150154132A1 (en) * 2013-12-02 2015-06-04 Sandisk Technologies Inc. System and method of arbitration associated with a multi-threaded system
CN103914413A (zh) * 2014-04-18 2014-07-09 东南大学 用于粗粒度可重构系统的外存访问接口及其访问方法
US9209961B1 (en) 2014-09-29 2015-12-08 Apple Inc. Method and apparatus for delay compensation in data transmission
US9904645B2 (en) * 2014-10-31 2018-02-27 Texas Instruments Incorporated Multicore bus architecture with non-blocking high performance transaction credit system
US9684615B1 (en) * 2015-01-08 2017-06-20 Altera Corporation Apparatus and methods for multiple-channel direct memory access
CN112650355B (zh) 2015-07-20 2025-07-18 美国莱迪思半导体公司 低速总线时间戳记方法和电路
US9904635B2 (en) * 2015-08-27 2018-02-27 Samsung Electronics Co., Ltd. High performance transaction-based memory systems
US9934174B2 (en) * 2015-09-18 2018-04-03 Seagate Technology Llc Selectively enable data transfer based on accrued data credits
US10303631B2 (en) * 2016-03-17 2019-05-28 International Business Machines Corporation Self-moderating bus arbitration architecture
US10911261B2 (en) 2016-12-19 2021-02-02 Intel Corporation Method, apparatus and system for hierarchical network on chip routing
US10846126B2 (en) * 2016-12-28 2020-11-24 Intel Corporation Method, apparatus and system for handling non-posted memory write transactions in a fabric
CN111630471A (zh) 2017-03-06 2020-09-04 脸谱科技有限责任公司 在集成电路中的电路区域的操作点控制器
US11231769B2 (en) 2017-03-06 2022-01-25 Facebook Technologies, Llc Sequencer-based protocol adapter
US11080188B1 (en) 2018-03-28 2021-08-03 Apple Inc. Method to ensure forward progress of a processor in the presence of persistent external cache/TLB maintenance requests
US11269774B2 (en) 2018-10-15 2022-03-08 Texas Instruments Incorporated Delayed snoop for improved multi-process false sharing parallel thread performance
US12406174B2 (en) 2018-10-16 2025-09-02 International Business Machines Corporation Multi-agent instruction execution engine for neural inference processing
US11397809B2 (en) * 2019-09-23 2022-07-26 Stmicroelectronics International N.V. Protection scheme for sensor segmentation in virtualization application
US10972408B1 (en) 2020-02-10 2021-04-06 Apple Inc. Configurable packet arbitration with minimum progress guarantees
US11422946B2 (en) 2020-08-31 2022-08-23 Apple Inc. Translation lookaside buffer striping for efficient invalidation operations
US11615033B2 (en) 2020-09-09 2023-03-28 Apple Inc. Reducing translation lookaside buffer searches for splintered pages
US11675710B2 (en) 2020-09-09 2023-06-13 Apple Inc. Limiting translation lookaside buffer searches using active page size

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4897833A (en) * 1987-10-16 1990-01-30 Digital Equipment Corporation Hierarchical arbitration system
US4987833A (en) * 1988-03-28 1991-01-29 Antosh Mark J Solar induction monorail apparatus and method
US5392434A (en) * 1993-09-03 1995-02-21 Motorola, Inc. Arbitration protocol system granting use of a shared resource to one of a plurality of resource users
JP3525506B2 (ja) * 1994-09-02 2004-05-10 株式会社日立製作所 バスアービトレーション装置及び方法
EP0776504B1 (en) * 1995-05-26 2004-08-18 National Semiconductor Corporation Integrated circuit with multiple functions sharing multiple internal signal buses for distributing bus access control and arbitration control
EP0752666A3 (en) * 1995-07-06 2004-04-28 Sun Microsystems, Inc. Method and apparatus for fast-forwarding slave requests in a packet-switched computer system
JPH1196108A (ja) * 1997-09-18 1999-04-09 Toshiba Corp 計算機システム及びバス制御装置
JPH11191076A (ja) * 1997-12-26 1999-07-13 Fujitsu Ltd 情報処理装置
JP3071752B2 (ja) * 1998-03-24 2000-07-31 三菱電機株式会社 ブリッジ方法、バスブリッジ及びマルチプロセッサシステム
US6145032A (en) * 1998-09-21 2000-11-07 International Business Machines Corporation System for recirculation of communication transactions in data processing in the event of communication stall
US6434649B1 (en) * 1998-10-14 2002-08-13 Hitachi, Ltd. Data streamer
US6601151B1 (en) * 1999-02-08 2003-07-29 Sun Microsystems, Inc. Apparatus and method for handling memory access requests in a data processing system
KR100708096B1 (ko) * 2000-07-21 2007-04-16 삼성전자주식회사 버스 시스템 및 그 실행 순서 조정방법
US7028115B1 (en) 2000-10-06 2006-04-11 Broadcom Corporation Source triggered transaction blocking
US6622208B2 (en) * 2001-03-30 2003-09-16 Cirrus Logic, Inc. System and methods using a system-on-a-chip with soft cache
US6832279B1 (en) * 2001-05-17 2004-12-14 Cisco Systems, Inc. Apparatus and technique for maintaining order among requests directed to a same address on an external bus of an intermediate network node
US6829665B2 (en) * 2001-09-28 2004-12-07 Hewlett-Packard Development Company, L.P. Next snoop predictor in a host controller
DE60139260D1 (de) 2001-10-29 2009-08-27 Ericsson Telefon Ab L M Optimierung des Entwurfs einer synchronen digitalen Schaltung
US7539199B2 (en) * 2003-02-21 2009-05-26 Gireesh Shrimali Switch fabric scheduling with fairness and priority consideration
US7360008B2 (en) * 2004-12-30 2008-04-15 Intel Corporation Enforcing global ordering through a caching bridge in a multicore multiprocessor system

Also Published As

Publication number Publication date
US7970970B2 (en) 2011-06-28
US7461190B2 (en) 2008-12-02
EP1922629B1 (en) 2010-11-24
US20100235675A1 (en) 2010-09-16
US7752366B2 (en) 2010-07-06
US20090055568A1 (en) 2009-02-26
US20070038791A1 (en) 2007-02-15
DE602006018483D1 (de) 2011-01-05
CN101305354B (zh) 2011-08-31
JP4851523B2 (ja) 2012-01-11
EP1922629A1 (en) 2008-05-21
TWI396091B (zh) 2013-05-11
CN101305354A (zh) 2008-11-12
TW200809518A (en) 2008-02-16
ES2354748T3 (es) 2011-03-17
JP2009514065A (ja) 2009-04-02
WO2007022018A1 (en) 2007-02-22

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