JP4851523B2 - 浅いエージェント毎のキューを伴うブロックしないアドレス・スイッチ - Google Patents

浅いエージェント毎のキューを伴うブロックしないアドレス・スイッチ Download PDF

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Publication number
JP4851523B2
JP4851523B2 JP2008526262A JP2008526262A JP4851523B2 JP 4851523 B2 JP4851523 B2 JP 4851523B2 JP 2008526262 A JP2008526262 A JP 2008526262A JP 2008526262 A JP2008526262 A JP 2008526262A JP 4851523 B2 JP4851523 B2 JP 4851523B2
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Prior art keywords
request
switch
agent
agents
requests
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Japanese (ja)
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JP2009514065A5 (enExample
JP2009514065A (ja
Inventor
サブラマニアン，シュリダール・ピイ
ケラー，ジェイムズ・ビイ
イウ，ジョージ・コン
ワドハワン，ルチ
グンナ，ラメシュ
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Apple Inc
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Apple Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)
  • Measuring Or Testing Involving Enzymes Or Micro-Organisms (AREA)
JP2008526262A 2005-08-11 2006-08-11 浅いエージェント毎のキューを伴うブロックしないアドレス・スイッチ Expired - Fee Related JP4851523B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/201,581 US7461190B2 (en) 2005-08-11 2005-08-11 Non-blocking address switch with shallow per agent queues
US11/201,581 2005-08-11
PCT/US2006/031520 WO2007022018A1 (en) 2005-08-11 2006-08-11 Non-blocking address switch with shallow per agent queues

Publications (3)

Publication Number Publication Date
JP2009514065A JP2009514065A (ja) 2009-04-02
JP2009514065A5 JP2009514065A5 (enExample) 2009-09-17
JP4851523B2 true JP4851523B2 (ja) 2012-01-11

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JP2008526262A Expired - Fee Related JP4851523B2 (ja) 2005-08-11 2006-08-11 浅いエージェント毎のキューを伴うブロックしないアドレス・スイッチ

Country Status (9)

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US (3) US7461190B2 (enExample)
EP (1) EP1922629B1 (enExample)
JP (1) JP4851523B2 (enExample)
CN (1) CN101305354B (enExample)
AT (1) ATE489678T1 (enExample)
DE (1) DE602006018483D1 (enExample)
ES (1) ES2354748T3 (enExample)
TW (1) TWI396091B (enExample)
WO (1) WO2007022018A1 (enExample)

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US9514074B2 (en) 2009-02-13 2016-12-06 The Regents Of The University Of Michigan Single cycle arbitration within an interconnect
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US8611335B1 (en) * 2009-08-13 2013-12-17 Google, Inc. System and method for assigning paths for data flows through a wide-area network
US8351594B2 (en) * 2010-02-08 2013-01-08 Genesys Telecommunications Laboratories, Inc. System for indicating priority levels for transaction and task engagement in a call center
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US8868855B2 (en) * 2011-02-28 2014-10-21 Hewlett-Packard Development Company, L.P. Request management system and method for dynamically managing prioritized requests
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US9021156B2 (en) 2011-08-31 2015-04-28 Prashanth Nimmala Integrating intellectual property (IP) blocks into a processor
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CN103024699B (zh) * 2011-09-22 2016-05-25 北京神州泰岳软件股份有限公司 一种短信发送方法和一种信息资源站实体
US8713240B2 (en) 2011-09-29 2014-04-29 Intel Corporation Providing multiple decode options for a system-on-chip (SoC) fabric
US8711875B2 (en) 2011-09-29 2014-04-29 Intel Corporation Aggregating completion messages in a sideband interface
US8929373B2 (en) 2011-09-29 2015-01-06 Intel Corporation Sending packets with expanded headers
US8713234B2 (en) * 2011-09-29 2014-04-29 Intel Corporation Supporting multiple channels of a single interface
US8775700B2 (en) 2011-09-29 2014-07-08 Intel Corporation Issuing requests to a fabric
US8874976B2 (en) 2011-09-29 2014-10-28 Intel Corporation Providing error handling support to legacy devices
US8805926B2 (en) 2011-09-29 2014-08-12 Intel Corporation Common idle state, active state and credit management for an interface
US9053251B2 (en) 2011-11-29 2015-06-09 Intel Corporation Providing a sideband message interface for system on a chip (SoC)
US8856415B2 (en) * 2012-02-01 2014-10-07 National Instruments Corporation Bus arbitration for a real-time computer system
US8904451B2 (en) * 2012-04-13 2014-12-02 Theplatform, Llc Systems for prioritizing video processing events based on availability of media file and agent to process the event type
US8982695B2 (en) * 2012-09-29 2015-03-17 Intel Corporation Anti-starvation and bounce-reduction mechanism for a two-dimensional bufferless interconnect
US20150154132A1 (en) * 2013-12-02 2015-06-04 Sandisk Technologies Inc. System and method of arbitration associated with a multi-threaded system
CN103914413A (zh) * 2014-04-18 2014-07-09 东南大学 用于粗粒度可重构系统的外存访问接口及其访问方法
US9209961B1 (en) 2014-09-29 2015-12-08 Apple Inc. Method and apparatus for delay compensation in data transmission
US9904645B2 (en) * 2014-10-31 2018-02-27 Texas Instruments Incorporated Multicore bus architecture with non-blocking high performance transaction credit system
US9684615B1 (en) * 2015-01-08 2017-06-20 Altera Corporation Apparatus and methods for multiple-channel direct memory access
CN112650355B (zh) 2015-07-20 2025-07-18 美国莱迪思半导体公司 低速总线时间戳记方法和电路
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US9934174B2 (en) * 2015-09-18 2018-04-03 Seagate Technology Llc Selectively enable data transfer based on accrued data credits
US10303631B2 (en) * 2016-03-17 2019-05-28 International Business Machines Corporation Self-moderating bus arbitration architecture
US10911261B2 (en) 2016-12-19 2021-02-02 Intel Corporation Method, apparatus and system for hierarchical network on chip routing
US10846126B2 (en) * 2016-12-28 2020-11-24 Intel Corporation Method, apparatus and system for handling non-posted memory write transactions in a fabric
CN111630471A (zh) 2017-03-06 2020-09-04 脸谱科技有限责任公司 在集成电路中的电路区域的操作点控制器
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US11269774B2 (en) 2018-10-15 2022-03-08 Texas Instruments Incorporated Delayed snoop for improved multi-process false sharing parallel thread performance
US12406174B2 (en) 2018-10-16 2025-09-02 International Business Machines Corporation Multi-agent instruction execution engine for neural inference processing
US11397809B2 (en) * 2019-09-23 2022-07-26 Stmicroelectronics International N.V. Protection scheme for sensor segmentation in virtualization application
US10972408B1 (en) 2020-02-10 2021-04-06 Apple Inc. Configurable packet arbitration with minimum progress guarantees
US11422946B2 (en) 2020-08-31 2022-08-23 Apple Inc. Translation lookaside buffer striping for efficient invalidation operations
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Citations (6)

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JPH0877104A (ja) * 1994-09-02 1996-03-22 Hitachi Ltd バスアービトレーション装置及び方法
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Also Published As

Publication number Publication date
ATE489678T1 (de) 2010-12-15
US7970970B2 (en) 2011-06-28
US7461190B2 (en) 2008-12-02
EP1922629B1 (en) 2010-11-24
US20100235675A1 (en) 2010-09-16
US7752366B2 (en) 2010-07-06
US20090055568A1 (en) 2009-02-26
US20070038791A1 (en) 2007-02-15
DE602006018483D1 (de) 2011-01-05
CN101305354B (zh) 2011-08-31
EP1922629A1 (en) 2008-05-21
TWI396091B (zh) 2013-05-11
CN101305354A (zh) 2008-11-12
TW200809518A (en) 2008-02-16
ES2354748T3 (es) 2011-03-17
JP2009514065A (ja) 2009-04-02
WO2007022018A1 (en) 2007-02-22

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