DE60139260D1 - Optimierung des Entwurfs einer synchronen digitalen Schaltung - Google Patents

Optimierung des Entwurfs einer synchronen digitalen Schaltung

Info

Publication number
DE60139260D1
DE60139260D1 DE60139260T DE60139260T DE60139260D1 DE 60139260 D1 DE60139260 D1 DE 60139260D1 DE 60139260 T DE60139260 T DE 60139260T DE 60139260 T DE60139260 T DE 60139260T DE 60139260 D1 DE60139260 D1 DE 60139260D1
Authority
DE
Germany
Prior art keywords
optimizing
design
digital circuit
synchronous digital
synchronous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60139260T
Other languages
English (en)
Inventor
Hans Lindkvist
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Application granted granted Critical
Publication of DE60139260D1 publication Critical patent/DE60139260D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
DE60139260T 2001-10-29 2001-10-29 Optimierung des Entwurfs einer synchronen digitalen Schaltung Expired - Fee Related DE60139260D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP01610111A EP1308862B1 (de) 2001-10-29 2001-10-29 Optimierung des Entwurfs einer synchronen digitalen Schaltung

Publications (1)

Publication Number Publication Date
DE60139260D1 true DE60139260D1 (de) 2009-08-27

Family

ID=8183564

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60139260T Expired - Fee Related DE60139260D1 (de) 2001-10-29 2001-10-29 Optimierung des Entwurfs einer synchronen digitalen Schaltung

Country Status (2)

Country Link
EP (1) EP1308862B1 (de)
DE (1) DE60139260D1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7461190B2 (en) * 2005-08-11 2008-12-02 P.A. Semi, Inc. Non-blocking address switch with shallow per agent queues
US9176913B2 (en) 2011-09-07 2015-11-03 Apple Inc. Coherence switch for I/O traffic
CN110135098B (zh) * 2019-05-23 2023-04-07 中国科学院微电子研究所 一种亚阈值电路设计的优化方法及装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2677256B2 (ja) * 1995-06-26 1997-11-17 日本電気株式会社 遅延最適化方法
US5983007A (en) * 1996-11-25 1999-11-09 Lucent Technologies Inc. Low power circuits through hazard pulse suppression
SE516166C2 (sv) * 1999-06-04 2001-11-26 Ericsson Telefon Ab L M En anordning och ett förfarande relaterande till timing av kretsar
JP2001188819A (ja) * 2000-01-04 2001-07-10 Toshiba Microelectronics Corp ホールド違反改善方法、半導体集積回路、及びコンピュータ読み出し可能な記憶媒体
JP3317948B2 (ja) * 2000-01-20 2002-08-26 エヌイーシーマイクロシステム株式会社 半導体集積回路のレイアウト設計方法及び半導体集積回路

Also Published As

Publication number Publication date
EP1308862A1 (de) 2003-05-07
EP1308862B1 (de) 2009-07-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee