ATE464572T1 - Integrierte schaltungsanordnung und entwurfsverfahren - Google Patents
Integrierte schaltungsanordnung und entwurfsverfahrenInfo
- Publication number
- ATE464572T1 ATE464572T1 AT06809673T AT06809673T ATE464572T1 AT E464572 T1 ATE464572 T1 AT E464572T1 AT 06809673 T AT06809673 T AT 06809673T AT 06809673 T AT06809673 T AT 06809673T AT E464572 T1 ATE464572 T1 AT E464572T1
- Authority
- AT
- Austria
- Prior art keywords
- integrated circuit
- compaction
- network
- test
- circuit arrangement
- Prior art date
Links
- 238000005056 compaction Methods 0.000 abstract 6
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31703—Comparison aspects, e.g. signature analysis, comparators
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
- G01R31/31932—Comparators
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05110725 | 2005-11-14 | ||
PCT/IB2006/053895 WO2007054845A2 (en) | 2005-11-14 | 2006-10-23 | Integrated circuit arrangement and design method |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE464572T1 true ATE464572T1 (de) | 2010-04-15 |
Family
ID=37946470
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT06809673T ATE464572T1 (de) | 2005-11-14 | 2006-10-23 | Integrierte schaltungsanordnung und entwurfsverfahren |
Country Status (8)
Country | Link |
---|---|
US (1) | US7945828B2 (de) |
EP (1) | EP1952168B1 (de) |
JP (1) | JP2009516164A (de) |
CN (1) | CN101310191B (de) |
AT (1) | ATE464572T1 (de) |
DE (1) | DE602006013690D1 (de) |
TW (1) | TW200736629A (de) |
WO (1) | WO2007054845A2 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090150112A1 (en) * | 2007-12-05 | 2009-06-11 | Sun Microsystems, Inc. | Scan method and system of testing chip having multiple cores |
US9523736B2 (en) * | 2014-06-19 | 2016-12-20 | Nuvoton Technology Corporation | Detection of fault injection attacks using high-fanout networks |
CN104122497B (zh) * | 2014-08-11 | 2016-09-21 | 中国科学院自动化研究所 | 集成电路内建自测试所需测试向量的生成电路及方法 |
CN108872837A (zh) * | 2018-08-28 | 2018-11-23 | 长鑫存储技术有限公司 | 数据压缩电路、存储器、集成电路测试装置及测试方法 |
CN111175635B (zh) * | 2019-12-31 | 2021-12-03 | 中国电子产品可靠性与环境试验研究所((工业和信息化部电子第五研究所)(中国赛宝实验室)) | 集成电路测试装置 |
TWI783555B (zh) * | 2021-06-28 | 2022-11-11 | 瑞昱半導體股份有限公司 | 半導體裝置與測試脈衝訊號產生方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7552373B2 (en) * | 2002-01-16 | 2009-06-23 | Syntest Technologies, Inc. | Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit |
US7243110B2 (en) * | 2004-02-20 | 2007-07-10 | Sand Technology Inc. | Searchable archive |
US7308634B2 (en) * | 2005-04-01 | 2007-12-11 | Kabushiki Kaisha Toshiba | Systems and methods for LBIST testing using multiple functional subphases |
-
2006
- 2006-10-23 JP JP2008539544A patent/JP2009516164A/ja not_active Withdrawn
- 2006-10-23 CN CN2006800423480A patent/CN101310191B/zh not_active Expired - Fee Related
- 2006-10-23 WO PCT/IB2006/053895 patent/WO2007054845A2/en active Application Filing
- 2006-10-23 EP EP06809673A patent/EP1952168B1/de not_active Not-in-force
- 2006-10-23 US US12/093,639 patent/US7945828B2/en not_active Expired - Fee Related
- 2006-10-23 DE DE602006013690T patent/DE602006013690D1/de active Active
- 2006-10-23 AT AT06809673T patent/ATE464572T1/de not_active IP Right Cessation
- 2006-11-10 TW TW095141800A patent/TW200736629A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
EP1952168A2 (de) | 2008-08-06 |
DE602006013690D1 (de) | 2010-05-27 |
CN101310191A (zh) | 2008-11-19 |
EP1952168B1 (de) | 2010-04-14 |
CN101310191B (zh) | 2011-04-20 |
WO2007054845A2 (en) | 2007-05-18 |
WO2007054845A3 (en) | 2007-08-02 |
TW200736629A (en) | 2007-10-01 |
JP2009516164A (ja) | 2009-04-16 |
US20090024893A1 (en) | 2009-01-22 |
US7945828B2 (en) | 2011-05-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |