DE602006006065D1 - Prüfen einer integrierten schaltung, die geheiminformationen enthält - Google Patents

Prüfen einer integrierten schaltung, die geheiminformationen enthält

Info

Publication number
DE602006006065D1
DE602006006065D1 DE602006006065T DE602006006065T DE602006006065D1 DE 602006006065 D1 DE602006006065 D1 DE 602006006065D1 DE 602006006065 T DE602006006065 T DE 602006006065T DE 602006006065 T DE602006006065 T DE 602006006065T DE 602006006065 D1 DE602006006065 D1 DE 602006006065D1
Authority
DE
Germany
Prior art keywords
fuse elements
circuit
integrated circuit
inspect
test access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006006065T
Other languages
English (en)
Inventor
Erik J Marinissen
Sandeepkumar Goel
Andre K Nieuwland
Hubertus G H Vermeulen
Hendrikus P E Vranken
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602006006065D1 publication Critical patent/DE602006006065D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Storage Device Security (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE602006006065T 2005-08-10 2006-08-09 Prüfen einer integrierten schaltung, die geheiminformationen enthält Active DE602006006065D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05107361 2005-08-10
PCT/IB2006/052746 WO2007017838A1 (en) 2005-08-10 2006-08-09 Testing of an integrated circuit that contains secret information

Publications (1)

Publication Number Publication Date
DE602006006065D1 true DE602006006065D1 (de) 2009-05-14

Family

ID=37508307

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006006065T Active DE602006006065D1 (de) 2005-08-10 2006-08-09 Prüfen einer integrierten schaltung, die geheiminformationen enthält

Country Status (7)

Country Link
US (1) US9041411B2 (de)
EP (1) EP1915632B1 (de)
JP (1) JP2009505205A (de)
CN (1) CN101238382B (de)
AT (1) ATE427501T1 (de)
DE (1) DE602006006065D1 (de)
WO (1) WO2007017838A1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9041411B2 (en) * 2005-08-10 2015-05-26 Nxp B.V. Testing of an integrated circuit that contains secret information
WO2010016004A1 (en) * 2008-08-08 2010-02-11 Nxp B.V. Circuit with testable circuit coupled to privileged information supply circuit
WO2010104543A2 (en) * 2008-12-31 2010-09-16 Arizona Board Of Regents, For And On Behalf Of Arizona State University Integrated circuits secure from invasion and methods of manufacturing the same
US8230495B2 (en) * 2009-03-27 2012-07-24 International Business Machines Corporation Method for security in electronically fused encryption keys
JP2010266417A (ja) * 2009-05-18 2010-11-25 Sony Corp 半導体集積回路、情報処理装置、および情報処理方法、並びにプログラム
CN102565684A (zh) * 2010-12-13 2012-07-11 上海华虹集成电路有限责任公司 基于安全的扫描链控制电路、扫描链测试电路及使用方法
US9222973B2 (en) * 2011-01-20 2015-12-29 International Business Machines Corporation Protecting chip settings using secured scan chains
US8775108B2 (en) * 2011-06-29 2014-07-08 Duke University Method and architecture for pre-bond probing of TSVs in 3D stacked integrated circuits
EP2677327A1 (de) * 2012-06-21 2013-12-25 Gemalto SA Verfahren zur Herstellung einer elektronischen Vorrichtung mit deaktiviertem Sensitivitätsmodus und Verfahren zum Umwandeln einer solchen elektronischen Vorrichtung zur Reaktivierung des Sensitivitätsmodus
US9188643B2 (en) * 2012-11-13 2015-11-17 Globalfoundries Inc. Flexible performance screen ring oscillator within a scan chain
US20140355658A1 (en) * 2013-05-30 2014-12-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Modal PAM2/PAM4 Divide By N (Div-N) Automatic Correlation Engine (ACE) For A Receiver
EP2911086A1 (de) * 2014-02-19 2015-08-26 Renesas Electronics Europe GmbH Integrierte Schaltung mit Aktivteile, bezogen auf intrinsische Eigenschaften
US9128151B1 (en) 2014-05-08 2015-09-08 International Business Machines Corporation Performance screen ring oscillator formed from paired scan chains
US9097765B1 (en) 2014-05-08 2015-08-04 International Business Machines Corporation Performance screen ring oscillator formed from multi-dimensional pairings of scan chains
CN106556792B (zh) * 2015-09-28 2021-03-19 恩智浦美国有限公司 能够进行安全扫描的集成电路
US10095889B2 (en) * 2016-03-04 2018-10-09 Altera Corporation Techniques for protecting security features of integrated circuits
US10168386B2 (en) 2017-01-13 2019-01-01 International Business Machines Corporation Scan chain latency reduction
US10481205B2 (en) 2017-07-27 2019-11-19 Seagate Technology Llc Robust secure testing of integrated circuits
US10527674B2 (en) 2017-08-21 2020-01-07 International Business Machines Corporation Circuit structures to resolve random testability
US20230288477A1 (en) * 2022-03-14 2023-09-14 Duke University Dynamic scan obfuscation for integrated circuit protections
CN117521168A (zh) * 2023-11-20 2024-02-06 海光云芯集成电路设计(上海)有限公司 芯片、芯片的信息安全保护方法及电子设备

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2656939B1 (fr) * 1990-01-09 1992-04-03 Sgs Thomson Microelectronics Verrous de securite pour circuit integre.
US5264742A (en) * 1990-01-09 1993-11-23 Sgs-Thomson Microelectronics, S.A. Security locks for integrated circuit
US5357572A (en) * 1992-09-22 1994-10-18 Hughes Aircraft Company Apparatus and method for sensitive circuit protection with set-scan testing
US5787091A (en) * 1995-06-13 1998-07-28 Texas Instruments Incorporated Shared redundancy programming of memory with plural access ports
US5898776A (en) * 1996-11-21 1999-04-27 Quicklogic Corporation Security antifuse that prevents readout of some but not other information from a programmed field programmable gate array
EP0992809A1 (de) * 1998-09-28 2000-04-12 Siemens Aktiengesellschaft Schaltungsanordnung mit deaktivierbarem Scanpfad
DE10056591A1 (de) * 2000-11-15 2002-05-23 Philips Corp Intellectual Pty Verfahren zum Schutz einer Schaltungsanordnung zum Verarbeiten von Daten
US6766486B2 (en) * 2000-12-05 2004-07-20 Intel Corporation Joint test action group (JTAG) tester, such as to test integrated circuits in parallel
US6948098B2 (en) * 2001-03-30 2005-09-20 Cirrus Logic, Inc. Circuits and methods for debugging an embedded processor and systems using the same
US7395435B2 (en) * 2002-09-20 2008-07-01 Atmel Corporation Secure memory device for smart cards
US9041411B2 (en) * 2005-08-10 2015-05-26 Nxp B.V. Testing of an integrated circuit that contains secret information
EP1917535B1 (de) * 2005-08-10 2010-05-19 Nxp B.V. Prüfen einer integrierten schaltung, die geheiminformationen enthält
US8281198B2 (en) * 2009-08-07 2012-10-02 Via Technologies, Inc. User-initiatable method for detecting re-grown fuses within a microprocessor

Also Published As

Publication number Publication date
US20100264932A1 (en) 2010-10-21
WO2007017838A1 (en) 2007-02-15
US9041411B2 (en) 2015-05-26
EP1915632A1 (de) 2008-04-30
CN101238382A (zh) 2008-08-06
EP1915632B1 (de) 2009-04-01
CN101238382B (zh) 2012-03-28
ATE427501T1 (de) 2009-04-15
JP2009505205A (ja) 2009-02-05

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Legal Events

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