ATE420373T1 - Schaltungsanordnung und verfahren zum prüfen einer in der schaltungsanordnung bereitgestellten anwendungsschaltung - Google Patents

Schaltungsanordnung und verfahren zum prüfen einer in der schaltungsanordnung bereitgestellten anwendungsschaltung

Info

Publication number
ATE420373T1
ATE420373T1 AT05752048T AT05752048T ATE420373T1 AT E420373 T1 ATE420373 T1 AT E420373T1 AT 05752048 T AT05752048 T AT 05752048T AT 05752048 T AT05752048 T AT 05752048T AT E420373 T1 ATE420373 T1 AT E420373T1
Authority
AT
Austria
Prior art keywords
circuit
test
testing
application circuit
application
Prior art date
Application number
AT05752048T
Other languages
English (en)
Inventor
M Wittke
F Hapke
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE420373T1 publication Critical patent/ATE420373T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3187—Built-in tests

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
AT05752048T 2004-06-30 2005-06-27 Schaltungsanordnung und verfahren zum prüfen einer in der schaltungsanordnung bereitgestellten anwendungsschaltung ATE420373T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04103081 2004-06-30

Publications (1)

Publication Number Publication Date
ATE420373T1 true ATE420373T1 (de) 2009-01-15

Family

ID=35648820

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05752048T ATE420373T1 (de) 2004-06-30 2005-06-27 Schaltungsanordnung und verfahren zum prüfen einer in der schaltungsanordnung bereitgestellten anwendungsschaltung

Country Status (7)

Country Link
US (1) US7870453B2 (de)
EP (1) EP1763677B1 (de)
JP (1) JP2008505310A (de)
CN (1) CN101014869A (de)
AT (1) ATE420373T1 (de)
DE (1) DE602005012266D1 (de)
WO (1) WO2006003596A2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008078229A1 (en) * 2006-12-20 2008-07-03 Nxp B.V. Bist integrated circuit testing
US8145442B2 (en) * 2009-01-30 2012-03-27 Synopsys, Inc. Fast and accurate estimation of gate output loading
CN101881812A (zh) * 2010-07-05 2010-11-10 中国人民解放军63908部队 一种混合模式的内建自测试系统及其方法
CN102226947B (zh) * 2011-04-02 2014-03-26 电子科技大学 一种基于线性反馈移位寄存器的可控测试向量发生器
US9495271B2 (en) * 2014-01-29 2016-11-15 Freescale Semiconductor, Inc. Statistical power indication monitor for purpose of measuring power consumption
EP3756020B1 (de) * 2018-03-22 2024-04-24 Siemens Industry Software Inc. Deterministischer sternförmiger eingebauter selbsttest

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6061818A (en) * 1997-05-08 2000-05-09 The Board Of Trustees Of The Leland Stanford Junior University Altering bit sequences to contain predetermined patterns
US6684358B1 (en) * 1999-11-23 2004-01-27 Janusz Rajski Decompressor/PRPG for applying pseudo-random and deterministic test patterns
US6510398B1 (en) * 2000-06-22 2003-01-21 Intel Corporation Constrained signature-based test
DE10038327A1 (de) 2000-08-05 2002-02-14 Philips Corp Intellectual Pty Integrierter Schaltkreis mit Selbsttest-Schaltung
US6671838B1 (en) * 2000-09-27 2003-12-30 International Business Machines Corporation Method and apparatus for programmable LBIST channel weighting
DE10110777A1 (de) 2001-03-07 2002-09-12 Philips Corp Intellectual Pty Anordnung und Verfahren zum Testen von integrierten Schaltkreisen
DE10201554A1 (de) * 2002-01-17 2003-08-21 Philips Intellectual Property Integrierter Schaltkreis mit Selbsttest-Schaltung
US6968489B2 (en) * 2002-01-23 2005-11-22 International Business Machines Corporation Pseudo random optimized built-in self-test
JP3672546B2 (ja) * 2002-09-11 2005-07-20 株式会社半導体理工学研究センター テストパターン発生器における最適初期値の決定方法および装置
US7302624B2 (en) * 2003-02-13 2007-11-27 Janusz Rajski Adaptive fault diagnosis of compressed test responses
US7437640B2 (en) * 2003-02-13 2008-10-14 Janusz Rajski Fault diagnosis of compressed test responses having one or more unknown states
US7296249B2 (en) * 2003-10-10 2007-11-13 Thomas Hans Rinderknecht Using constrained scan cells to test integrated circuits
US7055077B2 (en) * 2003-12-23 2006-05-30 Kabushiki Kaisha Toshiba Systems and methods for circuit testing
US7631237B2 (en) * 2005-05-23 2009-12-08 Kabushiki Kaisha Toshiba Multi-test method for using compare MISR

Also Published As

Publication number Publication date
WO2006003596A2 (en) 2006-01-12
JP2008505310A (ja) 2008-02-21
EP1763677A2 (de) 2007-03-21
CN101014869A (zh) 2007-08-08
DE602005012266D1 (de) 2009-02-26
US7870453B2 (en) 2011-01-11
WO2006003596A3 (en) 2006-05-11
EP1763677B1 (de) 2009-01-07
US20080195907A1 (en) 2008-08-14

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