ATE338979T1 - Adressenraum, bussystem, speicherungssteuerung und einrichtungssystem - Google Patents

Adressenraum, bussystem, speicherungssteuerung und einrichtungssystem

Info

Publication number
ATE338979T1
ATE338979T1 AT03737393T AT03737393T ATE338979T1 AT E338979 T1 ATE338979 T1 AT E338979T1 AT 03737393 T AT03737393 T AT 03737393T AT 03737393 T AT03737393 T AT 03737393T AT E338979 T1 ATE338979 T1 AT E338979T1
Authority
AT
Austria
Prior art keywords
memory
data
burst
memory devices
accessed
Prior art date
Application number
AT03737393T
Other languages
English (en)
Inventor
Egbert G T Jaspers
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE338979T1 publication Critical patent/ATE338979T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
AT03737393T 2002-02-06 2003-01-20 Adressenraum, bussystem, speicherungssteuerung und einrichtungssystem ATE338979T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02075502 2002-02-06

Publications (1)

Publication Number Publication Date
ATE338979T1 true ATE338979T1 (de) 2006-09-15

Family

ID=27675700

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03737393T ATE338979T1 (de) 2002-02-06 2003-01-20 Adressenraum, bussystem, speicherungssteuerung und einrichtungssystem

Country Status (8)

Country Link
US (1) US20050144369A1 (de)
EP (1) EP1474747B1 (de)
JP (1) JP2005517242A (de)
CN (1) CN100357923C (de)
AT (1) ATE338979T1 (de)
AU (1) AU2003201113A1 (de)
DE (1) DE60308150T2 (de)
WO (1) WO2003067445A1 (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7596139B2 (en) 2000-11-17 2009-09-29 Foundry Networks, Inc. Backplane interface adapter with error control and redundant fabric
US7236490B2 (en) 2000-11-17 2007-06-26 Foundry Networks, Inc. Backplane interface adapter
US7187687B1 (en) 2002-05-06 2007-03-06 Foundry Networks, Inc. Pipeline method and system for switching packets
US7649885B1 (en) 2002-05-06 2010-01-19 Foundry Networks, Inc. Network routing system for enhanced efficiency and monitoring capability
US20120155466A1 (en) 2002-05-06 2012-06-21 Ian Edward Davis Method and apparatus for efficiently processing data packets in a computer network
US7468975B1 (en) 2002-05-06 2008-12-23 Foundry Networks, Inc. Flexible method for processing data packets in a network routing system for enhanced efficiency and monitoring capability
US7266117B1 (en) 2002-05-06 2007-09-04 Foundry Networks, Inc. System architecture for very fast ethernet blade
US6901072B1 (en) 2003-05-15 2005-05-31 Foundry Networks, Inc. System and method for high speed packet transmission implementing dual transmit and receive pipelines
DE10323415A1 (de) * 2003-05-23 2004-12-30 Infineon Technologies Ag Speicheranordnung
US20050138276A1 (en) * 2003-12-17 2005-06-23 Intel Corporation Methods and apparatus for high bandwidth random access using dynamic random access memory
WO2005088468A2 (en) * 2004-03-10 2005-09-22 Koninklijke Philips Electronics N.V. Integrated circuit and method for memory access control
US7817659B2 (en) 2004-03-26 2010-10-19 Foundry Networks, Llc Method and apparatus for aggregating input data streams
US8730961B1 (en) 2004-04-26 2014-05-20 Foundry Networks, Llc System and method for optimizing router lookup
DE102004031715B4 (de) * 2004-06-30 2013-05-29 Globalfoundries Inc. Kombinierte On-Chip-Befehls- und Antwortdatenschnittstelle
US20060092320A1 (en) * 2004-10-29 2006-05-04 Nickerson Brian R Transferring a video frame from memory into an on-chip buffer for video processing
US7657703B1 (en) 2004-10-29 2010-02-02 Foundry Networks, Inc. Double density content addressable memory (CAM) lookup scheme
US7577763B1 (en) * 2005-02-28 2009-08-18 Apple Inc. Managing read requests from multiple requestors
KR100634566B1 (ko) * 2005-10-06 2006-10-16 엠텍비젼 주식회사 공유 메모리 제어 방법 및 공유 메모리 동작 제어를수행하는 사용자 단말기
US8448162B2 (en) 2005-12-28 2013-05-21 Foundry Networks, Llc Hitless software upgrades
KR100748191B1 (ko) * 2006-04-06 2007-08-09 엠텍비젼 주식회사 공유 메모리를 구비한 장치 및 공유 메모리 억세스 상태정보 제공 방법
JP2008009564A (ja) * 2006-06-27 2008-01-17 Fujitsu Ltd メモリアクセス装置、メモリアクセス方法、メモリ製造方法およびプログラム
KR100782592B1 (ko) * 2006-08-10 2007-12-06 엠텍비젼 주식회사 공유 메모리를 구비한 장치 및 공유 메모리 제어 방법
US7903654B2 (en) 2006-08-22 2011-03-08 Foundry Networks, Llc System and method for ECMP load sharing
US8238255B2 (en) 2006-11-22 2012-08-07 Foundry Networks, Llc Recovering from failures without impact on data traffic in a shared bus architecture
KR20090065504A (ko) 2006-12-25 2009-06-22 파나소닉 주식회사 메모리 제어 장치, 메모리 장치 및 메모리 제어 방법
US8155011B2 (en) 2007-01-11 2012-04-10 Foundry Networks, Llc Techniques for using dual memory structures for processing failure detection protocol packets
US8271859B2 (en) 2007-07-18 2012-09-18 Foundry Networks Llc Segmented CRC design in high speed networks
US8037399B2 (en) 2007-07-18 2011-10-11 Foundry Networks, Llc Techniques for segmented CRC design in high speed networks
US8509236B2 (en) 2007-09-26 2013-08-13 Foundry Networks, Llc Techniques for selecting paths and/or trunk ports for forwarding traffic flows
CN101903868B (zh) * 2007-12-21 2012-07-04 松下电器产业株式会社 存储装置以及其控制方法
US8599850B2 (en) 2009-09-21 2013-12-03 Brocade Communications Systems, Inc. Provisioning single or multistage networks using ethernet service instances (ESIs)
DE102011108172B4 (de) 2011-07-22 2013-10-10 Texas Instruments Deutschland Gmbh Speichersystem und Verfahren zum Übermitteln von Konfigurationsbefehlen
WO2013016291A2 (en) * 2011-07-22 2013-01-31 Texas Instruments Incorporated Memory system and method for passing configuration commands
US8984203B2 (en) 2012-10-09 2015-03-17 Sandisk Technologies Inc. Memory access control module and associated methods
US10599580B2 (en) 2018-05-23 2020-03-24 International Business Machines Corporation Representing an address space of unequal granularity and alignment
CN113495684A (zh) * 2020-04-08 2021-10-12 华为技术有限公司 一种数据管理装置及数据管理方法、数据存储设备

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0642263B2 (ja) * 1984-11-26 1994-06-01 株式会社日立製作所 デ−タ処理装置
US5175835A (en) * 1990-01-10 1992-12-29 Unisys Corporation Multi-mode DRAM controller
US5479630A (en) * 1991-04-03 1995-12-26 Silicon Graphics Inc. Hybrid cache having physical-cache and virtual-cache characteristics and method for accessing same
GB2287808B (en) * 1994-03-24 1998-08-05 Discovision Ass Method and apparatus for interfacing with ram
US5537564A (en) * 1993-03-08 1996-07-16 Zilog, Inc. Technique for accessing and refreshing memory locations within electronic storage devices which need to be refreshed with minimum power consumption
US5640527A (en) * 1993-07-14 1997-06-17 Dell Usa, L.P. Apparatus and method for address pipelining of dynamic random access memory utilizing transparent page address latches to reduce wait states
US5732041A (en) * 1993-08-19 1998-03-24 Mmc Networks, Inc. Memory interface unit, shared memory switch system and associated method
DE4427042C2 (de) * 1994-07-29 1997-05-22 Siemens Ag Verfahren zur Steuerung einer Sequenz von Zugriffen eines Prozessors zu einem zugeordneten Speicher
US6188595B1 (en) * 1998-06-30 2001-02-13 Micron Technology, Inc. Memory architecture and addressing for optimized density in integrated circuit package or on circuit board
KR100282125B1 (ko) * 1998-08-04 2001-02-15 윤종용 버스트-타입의 랜덤 액세스 메모리 장치의 어드레스 발생 회로
US6496902B1 (en) * 1998-12-31 2002-12-17 Cray Inc. Vector and scalar data cache for a vector multiprocessor
US6446169B1 (en) * 1999-08-31 2002-09-03 Micron Technology, Inc. SRAM with tag and data arrays for private external microprocessor bus
JP3416083B2 (ja) * 1999-08-31 2003-06-16 株式会社日立製作所 半導体装置
US6415374B1 (en) * 2000-03-16 2002-07-02 Mosel Vitelic, Inc. System and method for supporting sequential burst counts in double data rate (DDR) synchronous dynamic random access memories (SDRAM)
KR100335504B1 (ko) * 2000-06-30 2002-05-09 윤종용 제어 및 어드레스 버스를 공유하는 2채널 메모리 시스템및 이에 채용되는 메모리 모듈
US6912173B2 (en) * 2001-06-29 2005-06-28 Broadcom Corporation Method and system for fast memory access
CN1280734C (zh) * 2001-09-07 2006-10-18 皇家菲利浦电子有限公司 用于分段存取控制的控制装置和方法和具有该控制装置的视频存储器装置

Also Published As

Publication number Publication date
CN1628293A (zh) 2005-06-15
AU2003201113A1 (en) 2003-09-02
EP1474747B1 (de) 2006-09-06
DE60308150D1 (de) 2006-10-19
CN100357923C (zh) 2007-12-26
DE60308150T2 (de) 2007-07-19
EP1474747A1 (de) 2004-11-10
WO2003067445A1 (en) 2003-08-14
US20050144369A1 (en) 2005-06-30
JP2005517242A (ja) 2005-06-09

Similar Documents

Publication Publication Date Title
ATE338979T1 (de) Adressenraum, bussystem, speicherungssteuerung und einrichtungssystem
AU2003213840A8 (en) Memory system with burst length shorter than prefetch length
EP2126919A4 (de) Speichersystem und verfahren mit flüchtigen und nichtflüchtigen speicheranordnungen auf derselben hierarchischen ebene
HK1140031A1 (en) Adaptive memory device and method for enhancing the performance of an external computing device
WO2005114669A3 (en) System and method for improving performance in computer memory systems supporting multiple memory access latencies
RU2015151127A (ru) Гибридное запоминающее устройство
WO2009134561A3 (en) Multi-processor flash memory storage device and management system
BR112015000525A2 (pt) módulo computacional híbrido
WO2007134319A3 (en) Multi-chip package for a flash memory
DE60232367D1 (de) Verfahren zum dynamischen einstellen einer speicherseitenschliess-strategie
MY137842A (en) Interface for a block addressable mass storage system
BRPI0807899A8 (pt) Método implementado por computador, módulo de alocação em estado sólido, meio de armazenamento legível por computador e sistema
HK1122620A1 (en) Flash memory management method and system, memory device and flash memory device
WO2004053698A3 (en) Improved tlb management for real-time applications
DE60202898D1 (de) Speicherzugriffsarbitrierung mit garantierter Datentransferrate
US20150052288A1 (en) Apparatuses and methods for providing data from a buffer
WO2007002445A3 (en) Memory micro-tiling speculative returns
US20150052299A1 (en) Apparatuses and methods for providing data to a configurable storage area
GB2432943A (en) Data transfer into a processor cache using a DMA controller in the processor
ATE388439T1 (de) Speicherschnittstelle für systeme mit mehreren prozessoren und einem speichersystem
TW200636481A (en) System having cache memory and method of accessing
TW200731068A (en) Storage of transformed units of data in a memory system having fixed sized storage blocks
DE602004010399D1 (de) Neuadressierbare virtuelle dma-steuer und statusregister
WO2003083661A8 (en) Memory-access management method and system for synchronous dynamic random-access memory or the like
TW200713325A (en) Semiconductor memory device

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties