ATE388439T1 - Speicherschnittstelle für systeme mit mehreren prozessoren und einem speichersystem - Google Patents

Speicherschnittstelle für systeme mit mehreren prozessoren und einem speichersystem

Info

Publication number
ATE388439T1
ATE388439T1 AT04765854T AT04765854T ATE388439T1 AT E388439 T1 ATE388439 T1 AT E388439T1 AT 04765854 T AT04765854 T AT 04765854T AT 04765854 T AT04765854 T AT 04765854T AT E388439 T1 ATE388439 T1 AT E388439T1
Authority
AT
Austria
Prior art keywords
cpu
memory
abstract
external memory
time slot
Prior art date
Application number
AT04765854T
Other languages
English (en)
Inventor
Fredrik Angsmark
Tord Nilsson
David Barrow
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Application granted granted Critical
Publication of ATE388439T1 publication Critical patent/ATE388439T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT04765854T 2003-10-08 2004-10-06 Speicherschnittstelle für systeme mit mehreren prozessoren und einem speichersystem ATE388439T1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US50950303P 2003-10-08 2003-10-08
US51007403P 2003-10-09 2003-10-09
US53096003P 2003-12-19 2003-12-19
US10/857,319 US20050080999A1 (en) 2003-10-08 2004-05-27 Memory interface for systems with multiple processors and one memory system

Publications (1)

Publication Number Publication Date
ATE388439T1 true ATE388439T1 (de) 2008-03-15

Family

ID=34427064

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04765854T ATE388439T1 (de) 2003-10-08 2004-10-06 Speicherschnittstelle für systeme mit mehreren prozessoren und einem speichersystem

Country Status (8)

Country Link
US (1) US20050080999A1 (de)
EP (1) EP1685484B1 (de)
JP (1) JP2007508607A (de)
KR (1) KR101050019B1 (de)
CN (1) CN1864140B (de)
AT (1) ATE388439T1 (de)
DE (1) DE602004012310T2 (de)
WO (1) WO2005041042A2 (de)

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DE102005038567A1 (de) * 2005-08-12 2007-02-15 Micronas Gmbh Multi-Prozessor-Architektur und Verfahren zum Steuern von Speicherzugriff bei einer Multi-Prozess-Architektur
US7647476B2 (en) * 2006-03-14 2010-01-12 Intel Corporation Common analog interface for multiple processor cores
US7752373B2 (en) * 2007-02-09 2010-07-06 Sigmatel, Inc. System and method for controlling memory operations
US8694737B2 (en) 2010-06-09 2014-04-08 Micron Technology, Inc. Persistent memory for processor main memory
US9448938B2 (en) 2010-06-09 2016-09-20 Micron Technology, Inc. Cache coherence protocol for persistent memories
US8799685B2 (en) * 2010-08-25 2014-08-05 Advanced Micro Devices, Inc. Circuits and methods for providing adjustable power consumption
US8613074B2 (en) 2010-09-30 2013-12-17 Micron Technology, Inc. Security protection for memory content of processor main memory
US20130117168A1 (en) 2011-11-04 2013-05-09 Mark Henrik Sandstrom Maximizing Throughput of Multi-user Parallel Data Processing Systems
US8789065B2 (en) 2012-06-08 2014-07-22 Throughputer, Inc. System and method for input data load adaptive parallel processing
US8561078B2 (en) * 2011-09-27 2013-10-15 Throughputer, Inc. Task switching and inter-task communications for multi-core processors
WO2012125149A1 (en) 2011-03-14 2012-09-20 Hewlett-Packard Development Company, L.P. Memory interface
CN103493022B (zh) * 2011-03-28 2016-05-04 富士通株式会社 多核处理器系统
US8683100B1 (en) 2011-06-21 2014-03-25 Netlogic Microsystems, Inc. Method and apparatus for handling data flow in a multi-chip environment using an interchip interface
US9448847B2 (en) 2011-07-15 2016-09-20 Throughputer, Inc. Concurrent program execution optimization
EP3005128B1 (de) 2013-05-30 2018-07-04 Hewlett-Packard Enterprise Development LP Getrennte speichersteuerungen zum zugriff auf daten in einem speicher
CN105612493A (zh) * 2013-09-30 2016-05-25 慧与发展有限责任合伙企业 编程存储器控制器以允许执行主动式存储器操作
US20220113879A1 (en) * 2020-10-14 2022-04-14 Microchip Technology Incorporated System with Increasing Protected Storage Area and Erase Protection

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JP3579461B2 (ja) * 1993-10-15 2004-10-20 株式会社ルネサステクノロジ データ処理システム及びデータ処理装置
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Also Published As

Publication number Publication date
KR101050019B1 (ko) 2011-07-19
EP1685484B1 (de) 2008-03-05
KR20060134923A (ko) 2006-12-28
WO2005041042A2 (en) 2005-05-06
EP1685484A2 (de) 2006-08-02
DE602004012310D1 (de) 2008-04-17
WO2005041042A3 (en) 2005-11-24
CN1864140B (zh) 2013-03-20
CN1864140A (zh) 2006-11-15
JP2007508607A (ja) 2007-04-05
DE602004012310T2 (de) 2009-03-19
US20050080999A1 (en) 2005-04-14

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