CN1864140B - 用于具有多个处理器和一个存储器系统的系统的存储器接口 - Google Patents
用于具有多个处理器和一个存储器系统的系统的存储器接口 Download PDFInfo
- Publication number
- CN1864140B CN1864140B CN2004800293261A CN200480029326A CN1864140B CN 1864140 B CN1864140 B CN 1864140B CN 2004800293261 A CN2004800293261 A CN 2004800293261A CN 200480029326 A CN200480029326 A CN 200480029326A CN 1864140 B CN1864140 B CN 1864140B
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- CN
- China
- Prior art keywords
- control processor
- external memory
- clock
- time slot
- memory storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 claims abstract description 32
- 230000001360 synchronised effect Effects 0.000 claims abstract description 25
- 230000005055 memory storage Effects 0.000 claims description 98
- 238000013475 authorization Methods 0.000 claims 2
- 230000006870 function Effects 0.000 description 8
- 230000008901 benefit Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
- G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
- G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
Abstract
Description
Claims (20)
Applications Claiming Priority (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US50950303P | 2003-10-08 | 2003-10-08 | |
US60/509,503 | 2003-10-08 | ||
US51007403P | 2003-10-09 | 2003-10-09 | |
US60/510,074 | 2003-10-09 | ||
US53096003P | 2003-12-19 | 2003-12-19 | |
US60/530,960 | 2003-12-19 | ||
US10/857,319 | 2004-05-27 | ||
US10/857,319 US20050080999A1 (en) | 2003-10-08 | 2004-05-27 | Memory interface for systems with multiple processors and one memory system |
PCT/EP2004/011163 WO2005041042A2 (en) | 2003-10-08 | 2004-10-06 | Memory interface for systems with multiple processors and one memory system |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1864140A CN1864140A (zh) | 2006-11-15 |
CN1864140B true CN1864140B (zh) | 2013-03-20 |
Family
ID=34427064
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2004800293261A Expired - Fee Related CN1864140B (zh) | 2003-10-08 | 2004-10-06 | 用于具有多个处理器和一个存储器系统的系统的存储器接口 |
Country Status (8)
Country | Link |
---|---|
US (1) | US20050080999A1 (zh) |
EP (1) | EP1685484B1 (zh) |
JP (1) | JP2007508607A (zh) |
KR (1) | KR101050019B1 (zh) |
CN (1) | CN1864140B (zh) |
AT (1) | ATE388439T1 (zh) |
DE (1) | DE602004012310T2 (zh) |
WO (1) | WO2005041042A2 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105612493A (zh) * | 2013-09-30 | 2016-05-25 | 慧与发展有限责任合伙企业 | 编程存储器控制器以允许执行主动式存储器操作 |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7409572B1 (en) * | 2003-12-05 | 2008-08-05 | Lsi Corporation | Low power memory controller with leaded double data rate DRAM package arranged on a two layer printed circuit board |
JP2007525114A (ja) * | 2004-01-29 | 2007-08-30 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | プログラマブルで一時停止可能なクロック発生ユニット |
DE102005038567A1 (de) * | 2005-08-12 | 2007-02-15 | Micronas Gmbh | Multi-Prozessor-Architektur und Verfahren zum Steuern von Speicherzugriff bei einer Multi-Prozess-Architektur |
US7647476B2 (en) * | 2006-03-14 | 2010-01-12 | Intel Corporation | Common analog interface for multiple processor cores |
US7752373B2 (en) * | 2007-02-09 | 2010-07-06 | Sigmatel, Inc. | System and method for controlling memory operations |
US8694737B2 (en) | 2010-06-09 | 2014-04-08 | Micron Technology, Inc. | Persistent memory for processor main memory |
US9448938B2 (en) | 2010-06-09 | 2016-09-20 | Micron Technology, Inc. | Cache coherence protocol for persistent memories |
US8799685B2 (en) * | 2010-08-25 | 2014-08-05 | Advanced Micro Devices, Inc. | Circuits and methods for providing adjustable power consumption |
US8613074B2 (en) | 2010-09-30 | 2013-12-17 | Micron Technology, Inc. | Security protection for memory content of processor main memory |
US20130117168A1 (en) | 2011-11-04 | 2013-05-09 | Mark Henrik Sandstrom | Maximizing Throughput of Multi-user Parallel Data Processing Systems |
US8561078B2 (en) * | 2011-09-27 | 2013-10-15 | Throughputer, Inc. | Task switching and inter-task communications for multi-core processors |
US8789065B2 (en) | 2012-06-08 | 2014-07-22 | Throughputer, Inc. | System and method for input data load adaptive parallel processing |
KR101527308B1 (ko) * | 2011-03-14 | 2015-06-09 | 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. | 메모리 인터페이스 |
WO2012131884A1 (ja) * | 2011-03-28 | 2012-10-04 | 富士通株式会社 | マルチコアプロセッサシステム |
US8683100B1 (en) | 2011-06-21 | 2014-03-25 | Netlogic Microsystems, Inc. | Method and apparatus for handling data flow in a multi-chip environment using an interchip interface |
US9448847B2 (en) | 2011-07-15 | 2016-09-20 | Throughputer, Inc. | Concurrent program execution optimization |
CN105339917A (zh) | 2013-05-30 | 2016-02-17 | 惠普发展公司,有限责任合伙企业 | 访问存储器中数据的分离的存储器控制器 |
US20220113879A1 (en) * | 2020-10-14 | 2022-04-14 | Microchip Technology Incorporated | System with Increasing Protected Storage Area and Erase Protection |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5960458A (en) * | 1995-08-28 | 1999-09-28 | Hitachi, Ltd. | Shared memory system |
US6266751B1 (en) * | 1997-11-14 | 2001-07-24 | Agere Systems Guardin Corp. | Continuously sliding window method and apparatus for sharing single-ported memory banks between two agents |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US857320A (en) * | 1906-03-19 | 1907-06-18 | George Ulett | Household-tool. |
US857522A (en) * | 1906-10-04 | 1907-06-18 | Dell Harding | Stovepipe-thimble and flue-stopper. |
JPS5434640A (en) * | 1977-08-23 | 1979-03-14 | Hitachi Ltd | Memory unit |
US4164787A (en) * | 1977-11-09 | 1979-08-14 | Bell Telephone Laboratories, Incorporated | Multiple microprocessor intercommunication arrangement |
JPS5953959A (ja) * | 1982-09-20 | 1984-03-28 | Nec Corp | 共有メモリ装置 |
JPS62297963A (ja) * | 1986-06-18 | 1987-12-25 | Fujitsu Ltd | タイムスロツト割り当て回路 |
US5010476A (en) * | 1986-06-20 | 1991-04-23 | International Business Machines Corporation | Time multiplexed system for tightly coupling pipelined processors to separate shared instruction and data storage units |
US5978831A (en) * | 1991-03-07 | 1999-11-02 | Lucent Technologies Inc. | Synchronous multiprocessor using tasks directly proportional in size to the individual processors rates |
FR2692698A1 (fr) * | 1992-06-19 | 1993-12-24 | Sgs Thomson Microelectronics | Procédé pour partager une mémoire à accès direct entre deux processeurs asynchrones et circuit électronique pour la mise en Óoeuvre de ce procédé. |
US5471588A (en) * | 1992-11-25 | 1995-11-28 | Zilog, Inc. | Technique and circuit for providing two or more processors with time multiplexed access to a shared system resource |
JP3579461B2 (ja) * | 1993-10-15 | 2004-10-20 | 株式会社ルネサステクノロジ | データ処理システム及びデータ処理装置 |
US6256745B1 (en) * | 1998-06-05 | 2001-07-03 | Intel Corporation | Processor having execution core sections operating at different clock rates |
US6891819B1 (en) * | 1997-09-05 | 2005-05-10 | Kabushiki Kaisha Toshiba | Mobile IP communications scheme incorporating individual user authentication |
JP2000267928A (ja) * | 1999-03-15 | 2000-09-29 | Matsushita Electric Ind Co Ltd | メモリ制御装置 |
US6473821B1 (en) * | 1999-12-21 | 2002-10-29 | Visteon Global Technologies, Inc. | Multiple processor interface, synchronization, and arbitration scheme using time multiplexed shared memory for real time systems |
US7996592B2 (en) * | 2001-05-02 | 2011-08-09 | Nvidia Corporation | Cross bar multipath resource controller system and method |
JP2003114825A (ja) * | 2001-10-04 | 2003-04-18 | Hitachi Ltd | メモリ制御方法、その制御方法を用いたメモリ制御回路、及びそのメモリ制御回路を搭載する集積回路 |
US6978389B2 (en) * | 2001-12-20 | 2005-12-20 | Texas Instruments Incorporated | Variable clocking in an embedded symmetric multiprocessor system |
CA2417581C (en) * | 2002-01-28 | 2008-04-01 | Research In Motion Limited | Multiple-processor wireless mobile communication device |
US20050010476A1 (en) * | 2003-07-07 | 2005-01-13 | Nubella, Inc. | Consumer specific marketing tool method and apparatus |
-
2004
- 2004-05-27 US US10/857,319 patent/US20050080999A1/en not_active Abandoned
- 2004-10-06 AT AT04765854T patent/ATE388439T1/de not_active IP Right Cessation
- 2004-10-06 WO PCT/EP2004/011163 patent/WO2005041042A2/en active IP Right Grant
- 2004-10-06 KR KR1020067006802A patent/KR101050019B1/ko not_active IP Right Cessation
- 2004-10-06 DE DE602004012310T patent/DE602004012310T2/de active Active
- 2004-10-06 CN CN2004800293261A patent/CN1864140B/zh not_active Expired - Fee Related
- 2004-10-06 EP EP04765854A patent/EP1685484B1/en not_active Not-in-force
- 2004-10-06 JP JP2006530103A patent/JP2007508607A/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5960458A (en) * | 1995-08-28 | 1999-09-28 | Hitachi, Ltd. | Shared memory system |
US6266751B1 (en) * | 1997-11-14 | 2001-07-24 | Agere Systems Guardin Corp. | Continuously sliding window method and apparatus for sharing single-ported memory banks between two agents |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105612493A (zh) * | 2013-09-30 | 2016-05-25 | 慧与发展有限责任合伙企业 | 编程存储器控制器以允许执行主动式存储器操作 |
Also Published As
Publication number | Publication date |
---|---|
ATE388439T1 (de) | 2008-03-15 |
WO2005041042A3 (en) | 2005-11-24 |
DE602004012310D1 (de) | 2008-04-17 |
CN1864140A (zh) | 2006-11-15 |
WO2005041042A2 (en) | 2005-05-06 |
EP1685484A2 (en) | 2006-08-02 |
US20050080999A1 (en) | 2005-04-14 |
DE602004012310T2 (de) | 2009-03-19 |
KR20060134923A (ko) | 2006-12-28 |
EP1685484B1 (en) | 2008-03-05 |
JP2007508607A (ja) | 2007-04-05 |
KR101050019B1 (ko) | 2011-07-19 |
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Owner name: CLUSTER CO., LTD. Free format text: FORMER OWNER: TELEFONAKTIEBOLAGET LM ERICSSON (SE) S-126 25 STOCKHOLM, SWEDEN Effective date: 20150507 Owner name: OPTIS WIRELESS TECHNOLOGY LLC Free format text: FORMER OWNER: CLUSTER CO., LTD. Effective date: 20150507 |
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Effective date of registration: 20150507 Address after: Texas, USA Patentee after: Telefonaktiebolaget LM Ericsson (publ) Address before: Delaware Patentee before: Clastres LLC Effective date of registration: 20150507 Address after: Delaware Patentee after: Clastres LLC Address before: Stockholm Patentee before: Telefonaktiebolaget LM Ericsson |
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CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130320 Termination date: 20171006 |
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CF01 | Termination of patent right due to non-payment of annual fee |