ATE329409T1 - Phasenregelschleife - Google Patents

Phasenregelschleife

Info

Publication number
ATE329409T1
ATE329409T1 AT01273456T AT01273456T ATE329409T1 AT E329409 T1 ATE329409 T1 AT E329409T1 AT 01273456 T AT01273456 T AT 01273456T AT 01273456 T AT01273456 T AT 01273456T AT E329409 T1 ATE329409 T1 AT E329409T1
Authority
AT
Austria
Prior art keywords
phase
locked loop
mode
register set
data defining
Prior art date
Application number
AT01273456T
Other languages
English (en)
Inventor
Alan Smith
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of ATE329409T1 publication Critical patent/ATE329409T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1077—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the phase or frequency detection means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
AT01273456T 2001-01-25 2001-12-18 Phasenregelschleife ATE329409T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB0101954.6A GB0101954D0 (en) 2001-01-25 2001-01-25 Phase-locked loop

Publications (1)

Publication Number Publication Date
ATE329409T1 true ATE329409T1 (de) 2006-06-15

Family

ID=9907507

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01273456T ATE329409T1 (de) 2001-01-25 2001-12-18 Phasenregelschleife

Country Status (14)

Country Link
US (1) US6965271B2 (de)
EP (1) EP1354407B1 (de)
JP (1) JP3836794B2 (de)
CN (1) CN1242556C (de)
AT (1) ATE329409T1 (de)
BR (1) BR0116823A (de)
CA (1) CA2435705C (de)
DE (1) DE60120490T2 (de)
DK (1) DK1354407T3 (de)
ES (1) ES2269308T3 (de)
GB (1) GB0101954D0 (de)
HK (1) HK1062087A1 (de)
IL (2) IL156972A0 (de)
WO (1) WO2002060064A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2003280497A1 (en) * 2002-06-28 2004-01-19 Advanced Micro Devices, Inc. Phase-locked loop with automatic frequency tuning
GB2393611B8 (en) 2002-09-26 2006-05-11 Qualcomm Inc Method of and apparatus for reducing frequency errors associated with an inter-system scan
JP2006005489A (ja) 2004-06-15 2006-01-05 Sharp Corp Ｐｌｌ回路および高周波受信装置
US8811915B2 (en) * 2005-03-04 2014-08-19 Psion Inc. Digital wireless narrow band radio
US8041972B2 (en) * 2006-04-04 2011-10-18 Qualcomm Incorporated Apparatus and method for setting wakeup times in a communication device based on estimated lock on time of frequency synthesizer

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3042374B2 (ja) * 1995-06-29 2000-05-15 日本電気株式会社 周波数シンセサイザ
EP0755120A1 (de) 1995-07-18 1997-01-22 Nec Corporation Phasenregelkreisschaltung
US6150891A (en) * 1998-05-29 2000-11-21 Silicon Laboratories, Inc. PLL synthesizer having phase shifted control signals
US6111807A (en) * 1998-07-17 2000-08-29 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device allowing easy and fast text
JP3851064B2 (ja) * 1999-06-30 2006-11-29 インフィネオン テクノロジース アクチエンゲゼルシャフト Ｐｌｌシンセサイザ
US6718473B1 (en) * 2000-09-26 2004-04-06 Sun Microsystems, Inc. Method and apparatus for reducing power consumption

Also Published As

Publication number Publication date
ES2269308T3 (es) 2007-04-01
CN1242556C (zh) 2006-02-15
CA2435705A1 (en) 2002-08-01
DK1354407T3 (da) 2006-10-09
DE60120490D1 (de) 2006-07-20
WO2002060064A3 (en) 2002-11-14
US6965271B2 (en) 2005-11-15
HK1062087A1 (en) 2004-10-15
EP1354407B1 (de) 2006-06-07
WO2002060064A2 (en) 2002-08-01
JP2004527936A (ja) 2004-09-09
BR0116823A (pt) 2004-01-27
CN1488194A (zh) 2004-04-07
EP1354407A2 (de) 2003-10-22
IL156972A0 (en) 2004-02-08
US20040113703A1 (en) 2004-06-17
JP3836794B2 (ja) 2006-10-25
CA2435705C (en) 2006-05-30
IL156972A (en) 2007-12-03
GB0101954D0 (en) 2001-03-14
DE60120490T2 (de) 2007-01-11

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties