ATE282856T1 - Symmetrisches mehrprozessorsystem mit vereinheitlichter umgebung und verteilten systemfunktionen - Google Patents

Symmetrisches mehrprozessorsystem mit vereinheitlichter umgebung und verteilten systemfunktionen

Info

Publication number
ATE282856T1
ATE282856T1 AT00202734T AT00202734T ATE282856T1 AT E282856 T1 ATE282856 T1 AT E282856T1 AT 00202734 T AT00202734 T AT 00202734T AT 00202734 T AT00202734 T AT 00202734T AT E282856 T1 ATE282856 T1 AT E282856T1
Authority
AT
Austria
Prior art keywords
cache
cache line
specified address
symmetric multi
writing
Prior art date
Application number
AT00202734T
Other languages
English (en)
Inventor
James Bertone
Bruno Diplacido
Thomas Joyce
Martin Massucci
Lance Mcnally
Thomas L Murray Jr
Chester Nibby Jr
Michelle Pence
Marc Sanfacon
Jian-Kuo Shen
Jeffrey Somers
G Lewis Steiner
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Application granted granted Critical
Publication of ATE282856T1 publication Critical patent/ATE282856T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment
    • G06F12/0661—Configuration or reconfiguration with centralised address assignment and decentralised selection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
AT00202734T 1993-04-30 1994-04-28 Symmetrisches mehrprozessorsystem mit vereinheitlichter umgebung und verteilten systemfunktionen ATE282856T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US5705293A 1993-04-30 1993-04-30

Publications (1)

Publication Number Publication Date
ATE282856T1 true ATE282856T1 (de) 2004-12-15

Family

ID=22008220

Family Applications (3)

Application Number Title Priority Date Filing Date
AT00202734T ATE282856T1 (de) 1993-04-30 1994-04-28 Symmetrisches mehrprozessorsystem mit vereinheitlichter umgebung und verteilten systemfunktionen
AT94915976T ATE208926T1 (de) 1993-04-30 1994-04-28 Adaptive speichersteureinrichtung für ein symmetrisches mehrprozessorsystem
AT00203455T ATE249643T1 (de) 1993-04-30 1994-04-28 Symmetrisches mehrprozessorsystem mit vereinheitlichter umgebung und verteilten systemfunktionen

Family Applications After (2)

Application Number Title Priority Date Filing Date
AT94915976T ATE208926T1 (de) 1993-04-30 1994-04-28 Adaptive speichersteureinrichtung für ein symmetrisches mehrprozessorsystem
AT00203455T ATE249643T1 (de) 1993-04-30 1994-04-28 Symmetrisches mehrprozessorsystem mit vereinheitlichter umgebung und verteilten systemfunktionen

Country Status (6)

Country Link
EP (4) EP1071018B1 (de)
JP (8) JP3255922B2 (de)
AT (3) ATE282856T1 (de)
CA (3) CA2138537C (de)
DE (3) DE69434144D1 (de)
WO (1) WO1994025914A2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1071018B1 (de) * 1993-04-30 2003-09-10 Packard Bell NEC, Inc. Symmetrisches Mehrprozessorsystem mit vereinheitlichter Umgebung und verteilten Systemfunktionen
US6282647B1 (en) * 1999-06-02 2001-08-28 Adaptec, Inc. Method for flashing a read only memory (ROM) chip of a host adapter with updated option ROM bios code
JP2006293969A (ja) * 2005-03-17 2006-10-26 Fujitsu Ltd データ転送装置
JP4443474B2 (ja) 2005-06-14 2010-03-31 株式会社ソニー・コンピュータエンタテインメント コマンド転送制御装置およびコマンド転送制御方法
JP5168800B2 (ja) * 2006-03-08 2013-03-27 富士通株式会社 マルチプロセッサシステム
JP5079342B2 (ja) 2007-01-22 2012-11-21 ルネサスエレクトロニクス株式会社 マルチプロセッサ装置
US7979616B2 (en) * 2007-06-22 2011-07-12 International Business Machines Corporation System and method for providing a configurable command sequence for a memory interface device

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4760515A (en) * 1985-10-28 1988-07-26 International Business Machines Corporation Arbitration apparatus for determining priority of access to a shared bus on a rotating priority basis
JPS6462741A (en) * 1987-09-02 1989-03-09 Mitsubishi Electric Corp Main storage device
JPH01102661A (ja) * 1987-10-15 1989-04-20 Hitachi Ltd 記憶装置のバンク制御方式
JPH0212541A (ja) * 1988-04-29 1990-01-17 Internatl Business Mach Corp <Ibm> コンピユーテイング・システム及びその動作方法
US5111423A (en) * 1988-07-21 1992-05-05 Altera Corporation Programmable interface for computer system peripheral circuit card
US5117350A (en) * 1988-12-15 1992-05-26 Flashpoint Computer Corporation Memory address mechanism in a distributed memory architecture
US5155824A (en) * 1989-05-15 1992-10-13 Motorola, Inc. System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address
JPH0373040A (ja) * 1989-08-14 1991-03-28 Nec Corp キャッシュメモリ
JPH03167649A (ja) * 1989-11-28 1991-07-19 Nec Corp ウエイト・サイクル制御装置
JPH0435540A (ja) * 1990-05-31 1992-02-06 Fujitsu Ltd バス調停装置
US5283877A (en) * 1990-07-17 1994-02-01 Sun Microsystems, Inc. Single in-line DRAM memory module including a memory controller and cross bar switches
US5522064A (en) * 1990-10-01 1996-05-28 International Business Machines Corporation Data processing apparatus for dynamically setting timings in a dynamic memory system
JPH0715665B2 (ja) * 1991-06-10 1995-02-22 インターナショナル・ビジネス・マシーンズ・コーポレイション パーソナルコンピユータ
US5327570A (en) * 1991-07-22 1994-07-05 International Business Machines Corporation Multiprocessor system having local write cache within each data processor node
EP1071018B1 (de) * 1993-04-30 2003-09-10 Packard Bell NEC, Inc. Symmetrisches Mehrprozessorsystem mit vereinheitlichter Umgebung und verteilten Systemfunktionen

Also Published As

Publication number Publication date
ATE249643T1 (de) 2003-09-15
JP3957240B2 (ja) 2007-08-15
EP0648355B1 (de) 2001-11-14
CA2138537A1 (en) 1994-04-28
JP2004280787A (ja) 2004-10-07
JP2004310794A (ja) 2004-11-04
JP4106664B2 (ja) 2008-06-25
DE69429059D1 (de) 2001-12-20
EP1071018A2 (de) 2001-01-24
JPH1153254A (ja) 1999-02-26
ATE208926T1 (de) 2001-11-15
EP1067459A3 (de) 2001-02-07
JP4209764B2 (ja) 2009-01-14
CA2215844A1 (en) 1994-11-10
JP3255922B2 (ja) 2002-02-12
JPH1185681A (ja) 1999-03-30
EP1056020B1 (de) 2004-11-17
EP1056020A2 (de) 2000-11-29
EP1056020A3 (de) 2001-12-05
JPH11338760A (ja) 1999-12-10
EP0648355A1 (de) 1995-04-19
CA2138537C (en) 2003-02-25
WO1994025914A3 (en) 1995-01-05
CA2215701C (en) 2002-02-26
EP1067459B1 (de) 2013-08-28
WO1994025914A2 (en) 1994-11-10
EP1071018A3 (de) 2001-02-07
CA2215701A1 (en) 1994-11-10
EP1071018B1 (de) 2003-09-10
DE69434144D1 (de) 2004-12-23
JP2006085728A (ja) 2006-03-30
JPH07508611A (ja) 1995-09-21
EP1067459A2 (de) 2001-01-10
DE69433147D1 (de) 2003-10-16
JPH11126183A (ja) 1999-05-11
CA2215844C (en) 2001-09-04

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