ATE259999T1 - Speicher ausführung von register-exchange traceback für gigabit ethernet sender-empfänger - Google Patents

Speicher ausführung von register-exchange traceback für gigabit ethernet sender-empfänger

Info

Publication number
ATE259999T1
ATE259999T1 AT00959756T AT00959756T ATE259999T1 AT E259999 T1 ATE259999 T1 AT E259999T1 AT 00959756 T AT00959756 T AT 00959756T AT 00959756 T AT00959756 T AT 00959756T AT E259999 T1 ATE259999 T1 AT E259999T1
Authority
AT
Austria
Prior art keywords
pointer
symbol
decoder
exchange
symbols
Prior art date
Application number
AT00959756T
Other languages
English (en)
Inventor
Christian Luetkemeyer
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of ATE259999T1 publication Critical patent/ATE259999T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
    • H03M13/4184—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using register-exchange
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
    • H03M13/4192—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using combined traceback and register-exchange
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6563—Implementations using multi-port memories
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Artificial Intelligence (AREA)
  • Error Detection And Correction (AREA)
  • Small-Scale Networks (AREA)
  • Interface Circuits In Exchanges (AREA)
AT00959756T 1999-08-31 2000-08-31 Speicher ausführung von register-exchange traceback für gigabit ethernet sender-empfänger ATE259999T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15167999P 1999-08-31 1999-08-31
PCT/US2000/024069 WO2001017116A1 (en) 1999-08-31 2000-08-31 Memory-based shuffle-exchange traceback for gigabit ethernet transceiver

Publications (1)

Publication Number Publication Date
ATE259999T1 true ATE259999T1 (de) 2004-03-15

Family

ID=22539800

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00959756T ATE259999T1 (de) 1999-08-31 2000-08-31 Speicher ausführung von register-exchange traceback für gigabit ethernet sender-empfänger

Country Status (6)

Country Link
US (2) US6598205B1 (de)
EP (1) EP1206842B1 (de)
AT (1) ATE259999T1 (de)
AU (1) AU7102100A (de)
DE (1) DE60008388T2 (de)
WO (1) WO2001017116A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6598205B1 (en) * 1999-08-31 2003-07-22 Broadcom Corporation Memory-based shuffle-exchange traceback for gigabit ethernet transceiver
US6920182B2 (en) 2001-01-09 2005-07-19 Microtune (Texas), L.P. Delta-sigma modulator system and method
US7149952B2 (en) * 2002-04-17 2006-12-12 Thomson Licensing Memory management algorithm for trellis decoders
US7467359B2 (en) * 2002-11-26 2008-12-16 Lsi Corporation Decoder using a memory for storing state metrics implementing a decoder trellis
US20040255230A1 (en) * 2003-06-10 2004-12-16 Inching Chen Configurable decoder
US8140947B2 (en) * 2005-09-30 2012-03-20 Agere Systems Inc. Method and apparatus for storing survivor paths in a Viterbi detector using systematic pointer exchange
US7673224B2 (en) * 2006-09-12 2010-03-02 Agere Systems Inc. Low power viterbi decoder using a novel register-exchange architecture
US8605099B2 (en) 2008-03-31 2013-12-10 Intel Corporation Partition-free multi-socket memory system architecture

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4823346A (en) * 1986-04-16 1989-04-18 Hitachi, Ltd. Maximum likelihood decoder
US4748626A (en) * 1987-01-28 1988-05-31 Racal Data Communications Inc. Viterbi decoder with reduced number of data move operations
JP2702831B2 (ja) * 1991-08-28 1998-01-26 松下電送株式会社 ヴィタビ復号法
JP3259297B2 (ja) * 1991-11-15 2002-02-25 ソニー株式会社 ビタビ復号装置
JPH05335972A (ja) * 1992-05-27 1993-12-17 Nec Corp ビタビ復号器
JP2768169B2 (ja) * 1992-09-22 1998-06-25 日本電気株式会社 データ伝送方式
US5651032A (en) * 1993-11-04 1997-07-22 Kabushiki Kaisha Toshiba Apparatus and method for trellis decoder
JPH07245635A (ja) * 1994-03-04 1995-09-19 Sony Corp 信号点マッピング方法および信号点検出方法
JP3241210B2 (ja) * 1994-06-23 2001-12-25 沖電気工業株式会社 ビタビ復号方法及びビタビ復号回路
US5841478A (en) * 1996-04-09 1998-11-24 Thomson Multimedia, S.A. Code sequence detection in a trellis decoder
US5881074A (en) * 1997-03-25 1999-03-09 Level One Communications, Inc. 1000base-t packetized trellis coder
US6590942B1 (en) * 1997-11-03 2003-07-08 Harris Corporation Least squares phase fit as frequency estimate
US6205187B1 (en) * 1997-12-12 2001-03-20 General Dynamics Government Systems Corporation Programmable signal decoder
US6598205B1 (en) * 1999-08-31 2003-07-22 Broadcom Corporation Memory-based shuffle-exchange traceback for gigabit ethernet transceiver

Also Published As

Publication number Publication date
US20040054957A1 (en) 2004-03-18
AU7102100A (en) 2001-03-26
DE60008388D1 (de) 2004-03-25
US7003718B2 (en) 2006-02-21
US6598205B1 (en) 2003-07-22
DE60008388T2 (de) 2004-07-15
EP1206842A1 (de) 2002-05-22
EP1206842B1 (de) 2004-02-18
WO2001017116A1 (en) 2001-03-08

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