ATE253237T1 - Speicherkarte, speicherzugriffsverfahren und speicherzugriffsanordnung - Google Patents

Speicherkarte, speicherzugriffsverfahren und speicherzugriffsanordnung

Info

Publication number
ATE253237T1
ATE253237T1 AT97111033T AT97111033T ATE253237T1 AT E253237 T1 ATE253237 T1 AT E253237T1 AT 97111033 T AT97111033 T AT 97111033T AT 97111033 T AT97111033 T AT 97111033T AT E253237 T1 ATE253237 T1 AT E253237T1
Authority
AT
Austria
Prior art keywords
address
memory
flash memory
memory access
cpu
Prior art date
Application number
AT97111033T
Other languages
English (en)
Inventor
Kenjiro Nishino
Original Assignee
Dux Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dux Inc filed Critical Dux Inc
Application granted granted Critical
Publication of ATE253237T1 publication Critical patent/ATE253237T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
  • Credit Cards Or The Like (AREA)
  • Debugging And Monitoring (AREA)
AT97111033T 1996-07-12 1997-07-02 Speicherkarte, speicherzugriffsverfahren und speicherzugriffsanordnung ATE253237T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18333096A JP3761635B2 (ja) 1996-07-12 1996-07-12 メモリボード、メモリアクセス方法及びメモリアクセス装置

Publications (1)

Publication Number Publication Date
ATE253237T1 true ATE253237T1 (de) 2003-11-15

Family

ID=16133834

Family Applications (1)

Application Number Title Priority Date Filing Date
AT97111033T ATE253237T1 (de) 1996-07-12 1997-07-02 Speicherkarte, speicherzugriffsverfahren und speicherzugriffsanordnung

Country Status (5)

Country Link
US (1) US5966727A (de)
EP (1) EP0818731B1 (de)
JP (1) JP3761635B2 (de)
AT (1) ATE253237T1 (de)
DE (1) DE69725790D1 (de)

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US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
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US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
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Also Published As

Publication number Publication date
JP3761635B2 (ja) 2006-03-29
EP0818731A1 (de) 1998-01-14
US5966727A (en) 1999-10-12
DE69725790D1 (de) 2003-12-04
EP0818731B1 (de) 2003-10-29
JPH1027128A (ja) 1998-01-27

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