JPS6482152A - Information processor - Google Patents

Information processor

Info

Publication number
JPS6482152A
JPS6482152A JP62240066A JP24006687A JPS6482152A JP S6482152 A JPS6482152 A JP S6482152A JP 62240066 A JP62240066 A JP 62240066A JP 24006687 A JP24006687 A JP 24006687A JP S6482152 A JPS6482152 A JP S6482152A
Authority
JP
Japan
Prior art keywords
stage
memory access
bypass
address
selects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62240066A
Other languages
Japanese (ja)
Inventor
Yoichi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62240066A priority Critical patent/JPS6482152A/en
Publication of JPS6482152A publication Critical patent/JPS6482152A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To shorten the executing time of a memory access caused by a real address produced from a microprogram by using a means which bypasses an address conversion stage. CONSTITUTION:A 1st selector 45 usually selects the real address outputted from an address conversion buffer 33 of an address conversion stage 30 via a connection 302 and then selects the logical address on a 1st bypass to send it to a register of a cache memory access stage 40 when an ATB bypass signal is received for indication of the bypass of the stage 30. A 2nd selector 44 usually selects the memory access request code passed through the stage 30 via a connection 301 and then selects the memory access request code set on a 1st bypass when the ATB bypass signal is received. In such a constitution, the stage 30 is bypassed and the information can be processed at high speed when a memory access request is produced by a real address requiring no conversion of addresses.
JP62240066A 1987-09-24 1987-09-24 Information processor Pending JPS6482152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62240066A JPS6482152A (en) 1987-09-24 1987-09-24 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62240066A JPS6482152A (en) 1987-09-24 1987-09-24 Information processor

Publications (1)

Publication Number Publication Date
JPS6482152A true JPS6482152A (en) 1989-03-28

Family

ID=17053981

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62240066A Pending JPS6482152A (en) 1987-09-24 1987-09-24 Information processor

Country Status (1)

Country Link
JP (1) JPS6482152A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04160637A (en) * 1990-10-25 1992-06-03 Nec Corp Microcomputer
US5195809A (en) * 1991-02-11 1993-03-23 Alfred Teves Gmbh Hydraulic brake system with devices for controlling both brake slip and traction slip
JP2009527861A (en) * 2006-02-23 2009-07-30 フリースケール セミコンダクター インコーポレイテッド Data processing system and method having address translation bypass

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04160637A (en) * 1990-10-25 1992-06-03 Nec Corp Microcomputer
US5195809A (en) * 1991-02-11 1993-03-23 Alfred Teves Gmbh Hydraulic brake system with devices for controlling both brake slip and traction slip
JP2009527861A (en) * 2006-02-23 2009-07-30 フリースケール セミコンダクター インコーポレイテッド Data processing system and method having address translation bypass

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