ATE245290T1 - Unterbrechungssteuerungsgeräte in symmetrischen mehrprozessorsystemen - Google Patents

Unterbrechungssteuerungsgeräte in symmetrischen mehrprozessorsystemen

Info

Publication number
ATE245290T1
ATE245290T1 AT95303292T AT95303292T ATE245290T1 AT E245290 T1 ATE245290 T1 AT E245290T1 AT 95303292 T AT95303292 T AT 95303292T AT 95303292 T AT95303292 T AT 95303292T AT E245290 T1 ATE245290 T1 AT E245290T1
Authority
AT
Austria
Prior art keywords
interrupt
control unit
interrupt control
central
processing units
Prior art date
Application number
AT95303292T
Other languages
English (en)
Inventor
Douglas Gephardt
James Macdonald
Rodney Schmidt
Rupaka Mahalingaiah
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/251,843 external-priority patent/US5555430A/en
Priority claimed from US08/251,849 external-priority patent/US5564060A/en
Priority claimed from US08/251,799 external-priority patent/US5568649A/en
Priority claimed from US08/252,086 external-priority patent/US5530891A/en
Priority claimed from US08/251,850 external-priority patent/US5613126A/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE245290T1 publication Critical patent/ATE245290T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Bus Control (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Hardware Redundancy (AREA)
AT95303292T 1994-05-31 1995-05-17 Unterbrechungssteuerungsgeräte in symmetrischen mehrprozessorsystemen ATE245290T1 (de)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US25228194A 1994-05-31 1994-05-31
US08/251,843 US5555430A (en) 1994-05-31 1994-05-31 Interrupt control architecture for symmetrical multiprocessing system
US08/251,849 US5564060A (en) 1994-05-31 1994-05-31 Interrupt handling mechanism to prevent spurious interrupts in a symmetrical multiprocessing system
US08/251,799 US5568649A (en) 1994-05-31 1994-05-31 Interrupt cascading and priority configuration for a symmetrical multiprocessing system
US08/252,086 US5530891A (en) 1994-05-31 1994-05-31 System management interrupt mechanism within a symmetrical multiprocessing system
US08/251,850 US5613126A (en) 1994-05-31 1994-05-31 Timer tick auto-chaining technique within a symmetrical multiprocessing system

Publications (1)

Publication Number Publication Date
ATE245290T1 true ATE245290T1 (de) 2003-08-15

Family

ID=27559387

Family Applications (1)

Application Number Title Priority Date Filing Date
AT95303292T ATE245290T1 (de) 1994-05-31 1995-05-17 Unterbrechungssteuerungsgeräte in symmetrischen mehrprozessorsystemen

Country Status (4)

Country Link
EP (1) EP0685798B1 (de)
JP (1) JP4250207B2 (de)
AT (1) ATE245290T1 (de)
DE (1) DE69531270T2 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5778236A (en) * 1996-05-17 1998-07-07 Advanced Micro Devices, Inc. Multiprocessing interrupt controller on I/O bus
US5944809A (en) * 1996-08-20 1999-08-31 Compaq Computer Corporation Method and apparatus for distributing interrupts in a symmetric multiprocessor system
EP0827085B1 (de) * 1996-08-20 2006-03-29 Compaq Computer Corporation Verfahren und Vorrichtung zur Unterbrechungsverteilung in einem skalierbaren symmetrischen Mehrprozessorsystem ohne die Busbreite oder das Busprotokoll zu verändern
US6219741B1 (en) * 1997-12-10 2001-04-17 Intel Corporation Transactions supporting interrupt destination redirection and level triggered interrupt semantics
US6418496B2 (en) * 1997-12-10 2002-07-09 Intel Corporation System and apparatus including lowest priority logic to select a processor to receive an interrupt message
US6185639B1 (en) * 1998-06-05 2001-02-06 International Business Machines Corporation System and method to reduce a computer system's interrupt processing overhead
GB2396445B (en) 2002-12-19 2005-12-21 Advanced Risc Mach Ltd An interrupt controller and interrupt controlling method for prioritizing interrupt requests generated by a plurality of interrupt sources
JP4609113B2 (ja) * 2005-03-01 2011-01-12 セイコーエプソン株式会社 プロセッサ
JP2007188398A (ja) 2006-01-16 2007-07-26 Seiko Epson Corp マルチプロセッサシステム、マルチプロセッサシステムの制御方法をコンピュータに実行させるためのプログラム。
CN101105691B (zh) * 2007-05-23 2010-12-01 深圳市合信自动化技术有限公司 输入输出扩展模块及可编程控制器系统
US7849247B2 (en) 2008-10-14 2010-12-07 Freescale Semiconductor, Inc. Interrupt controller for accelerated interrupt handling in a data processing system and method thereof
DE102008062692B4 (de) * 2008-12-17 2013-11-14 Texas Instruments Deutschland Gmbh Eingebettetes Mikrocontrollersystem und Verfahren zur Konfiguration eines eingebetteten Mikrocontrollersystems mit gesteuertem Schaltmodus
US7996595B2 (en) 2009-04-14 2011-08-09 Lstar Technologies Llc Interrupt arbitration for multiprocessors
US8260996B2 (en) 2009-04-24 2012-09-04 Empire Technology Development Llc Interrupt optimization for multiprocessors
US8321614B2 (en) 2009-04-24 2012-11-27 Empire Technology Development Llc Dynamic scheduling interrupt controller for multiprocessors
US8234431B2 (en) 2009-10-13 2012-07-31 Empire Technology Development Llc Interrupt masking for multi-core processors
JP5522178B2 (ja) 2009-12-07 2014-06-18 富士通株式会社 情報システム
US9665509B2 (en) * 2014-08-20 2017-05-30 Xilinx, Inc. Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system
US10733141B2 (en) 2018-03-27 2020-08-04 Analog Devices, Inc. Distributed processor system
CN113614671B (zh) * 2019-04-04 2024-11-26 三菱电机株式会社 集中管理装置、设备控制系统及控制方法
CN113238802A (zh) * 2021-05-28 2021-08-10 上海阵量智能科技有限公司 中断分发器、数据处理芯片、中断分发及数据处理方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2855298B2 (ja) * 1990-12-21 1999-02-10 インテル・コーポレーション 割込み要求の仲裁方法およびマルチプロセッサシステム
EP0535821B1 (de) * 1991-09-27 1997-11-26 Sun Microsystems, Inc. Verfahren und Gerät für die dynamische Zuweisung von unadressierten Unterbrechungen
US5437042A (en) * 1992-10-02 1995-07-25 Compaq Computer Corporation Arrangement of DMA, interrupt and timer functions to implement symmetrical processing in a multiprocessor computer system
US5367689A (en) * 1992-10-02 1994-11-22 Compaq Computer Corporation Apparatus for strictly ordered input/output operations for interrupt system integrity

Also Published As

Publication number Publication date
DE69531270D1 (de) 2003-08-21
EP0685798A2 (de) 1995-12-06
DE69531270T2 (de) 2004-04-22
JPH0855038A (ja) 1996-02-27
EP0685798B1 (de) 2003-07-16
JP4250207B2 (ja) 2009-04-08
EP0685798A3 (de) 1997-05-07

Similar Documents

Publication Publication Date Title
ATE245290T1 (de) Unterbrechungssteuerungsgeräte in symmetrischen mehrprozessorsystemen
ATE202425T1 (de) Unterbrechungssystem in einem mikroprozessor
ATE233934T1 (de) Leistungssteuerungssystem für rechner
DE3688363D1 (de) Unterbrechungsabwicklung in einem multiprozessorrechnersystem.
JPH0534699B2 (de)
KR100376056B1 (ko) 멀티 프로세서 인터럽트 처리장치
JPH0644234B2 (ja) タスク管理装置
JPS6010383A (ja) マルチプロセツサシステムにおける負荷分散制御方式
JPS59135526A (ja) デ−タ入力制御方式
JPS56140429A (en) Advanced processing system for power supply abnormality in multiprocessor processing system
SU1084795A1 (ru) Устройство прерывани
JPS57139836A (en) Bus controlling system
JPS5518720A (en) Multiple computer system
JPS55121553A (en) Priority control system of electronic computer system
JPS633328B2 (de)
JPS6020273A (ja) デ−タ転送方式
KR970002673A (ko) 프로그램어블 인터럽트 콘트롤 장치
JPS61136115A (ja) マイクロコンピユ−タシステムの基本クロツク発生回路
JPS61166631A (ja) マイクロプログラム制御処理方法
JPH0381834A (ja) 割込み制御装置
JPS6041786B2 (ja) 割込制御システム
JPH04359629A (ja) 無矛盾性管理方式
JPH0644178A (ja) 割込み制御装置
JPS56145452A (en) Control system for power source fault of multiprocessor processing system
JPH03164940A (ja) 割込み時期を複数化した計算機

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties