ATE231258T1 - System zur durchführung eines hochgeschwindigkeitsperipheriebus - Google Patents

System zur durchführung eines hochgeschwindigkeitsperipheriebus

Info

Publication number
ATE231258T1
ATE231258T1 AT95305759T AT95305759T ATE231258T1 AT E231258 T1 ATE231258 T1 AT E231258T1 AT 95305759 T AT95305759 T AT 95305759T AT 95305759 T AT95305759 T AT 95305759T AT E231258 T1 ATE231258 T1 AT E231258T1
Authority
AT
Austria
Prior art keywords
high frequency
enable line
frequency operation
support high
bus
Prior art date
Application number
AT95305759T
Other languages
English (en)
Inventor
Sherman Lee
Michael T Wisor
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE231258T1 publication Critical patent/ATE231258T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
  • Facsimiles In General (AREA)
AT95305759T 1994-09-19 1995-08-17 System zur durchführung eines hochgeschwindigkeitsperipheriebus ATE231258T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/308,151 US5678065A (en) 1994-09-19 1994-09-19 Computer system employing an enable line for selectively adjusting a peripheral bus clock frequency

Publications (1)

Publication Number Publication Date
ATE231258T1 true ATE231258T1 (de) 2003-02-15

Family

ID=23192776

Family Applications (1)

Application Number Title Priority Date Filing Date
AT95305759T ATE231258T1 (de) 1994-09-19 1995-08-17 System zur durchführung eines hochgeschwindigkeitsperipheriebus

Country Status (5)

Country Link
US (2) US5678065A (de)
EP (1) EP0702308B1 (de)
JP (1) JPH08180013A (de)
AT (1) ATE231258T1 (de)
DE (1) DE69529375T2 (de)

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US6611891B1 (en) * 1998-11-23 2003-08-26 Advanced Micro Devices, Inc. Computer resource configuration mechanism across a multi-pipe communication link
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US6680631B2 (en) 2001-03-27 2004-01-20 Intel Corporation Setting the speed of clocked circuitry
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US6941483B2 (en) * 2001-12-31 2005-09-06 Hewlett-Packard Development Company, L.P. Bus capability voting mechanism
US6959395B2 (en) * 2002-06-26 2005-10-25 Broadcom Corporation Method and apparatus for the conditional enablement of PCI power management
US6954813B2 (en) * 2002-12-18 2005-10-11 International Business Machines Corporation Method, system and program product for facilitating hotplugging of multiple adapters into a system bus and transparently optimizing configuration of the system bus
US7206960B2 (en) * 2003-08-22 2007-04-17 Hewlett-Packard Development Company, L.P. Bus clock frequency management based on device load
US7146519B2 (en) * 2003-08-22 2006-12-05 Hewlett-Packard Development Company, L.P. Bus clock frequency management based on device bandwidth characteristics
US7149913B2 (en) 2003-08-22 2006-12-12 Hewlett-Packard Development Company, L.P. Bus clock frequency management based on characteristics of an application program
US7392445B2 (en) * 2003-09-11 2008-06-24 International Business Machines Corporation Autonomic bus reconfiguration for fault conditions
US7315957B1 (en) 2003-12-18 2008-01-01 Nvidia Corporation Method of providing a second clock while changing a first supplied clock frequency then supplying the changed first clock
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US7606960B2 (en) * 2004-03-26 2009-10-20 Intel Corporation Apparatus for adjusting a clock frequency of a variable speed bus
US9262837B2 (en) 2005-10-17 2016-02-16 Nvidia Corporation PCIE clock rate stepping for graphics and platform processors
JP4915113B2 (ja) * 2006-03-15 2012-04-11 日本電気株式会社 バスシステム、リセットイニシャライズ回路、及びバスシステムにおける障害復旧方法
KR100764686B1 (ko) * 2007-01-26 2007-10-08 주식회사 유비콘테크놀로지 시스템온칩의 클럭발생 제어장치
KR100736653B1 (ko) * 2007-01-26 2007-07-09 주식회사 유비콘테크놀로지 시스템온칩의 인터페이스 장치
US8015428B2 (en) * 2007-06-12 2011-09-06 Renesas Electronics Corporation Processing device and clock control method
JP5244037B2 (ja) * 2008-07-15 2013-07-24 パナソニック株式会社 メモリデバイス、メモリデバイス制御装置
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US9690726B2 (en) * 2014-11-11 2017-06-27 Atmel Corporation Peripheral register parameter refreshing
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Also Published As

Publication number Publication date
DE69529375T2 (de) 2003-10-23
EP0702308A1 (de) 1996-03-20
DE69529375D1 (de) 2003-02-20
US5678065A (en) 1997-10-14
JPH08180013A (ja) 1996-07-12
US5815734A (en) 1998-09-29
EP0702308B1 (de) 2003-01-15

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