ATE187845T1 - Verfahren zur isolierung von halbleiteranordnungen in einem substrat - Google Patents

Verfahren zur isolierung von halbleiteranordnungen in einem substrat

Info

Publication number
ATE187845T1
ATE187845T1 AT87302574T AT87302574T ATE187845T1 AT E187845 T1 ATE187845 T1 AT E187845T1 AT 87302574 T AT87302574 T AT 87302574T AT 87302574 T AT87302574 T AT 87302574T AT E187845 T1 ATE187845 T1 AT E187845T1
Authority
AT
Austria
Prior art keywords
substrate
regions
mask
mesa structures
epitaxial layer
Prior art date
Application number
AT87302574T
Other languages
English (en)
Inventor
Mammen Thomas
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE187845T1 publication Critical patent/ATE187845T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/76208—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region using auxiliary pillars in the recessed region, e.g. to form LOCOS over extended areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
AT87302574T 1986-03-27 1987-03-25 Verfahren zur isolierung von halbleiteranordnungen in einem substrat ATE187845T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/844,908 US4696095A (en) 1986-03-27 1986-03-27 Process for isolation using self-aligned diffusion process

Publications (1)

Publication Number Publication Date
ATE187845T1 true ATE187845T1 (de) 2000-01-15

Family

ID=25293937

Family Applications (1)

Application Number Title Priority Date Filing Date
AT87302574T ATE187845T1 (de) 1986-03-27 1987-03-25 Verfahren zur isolierung von halbleiteranordnungen in einem substrat

Country Status (5)

Country Link
US (1) US4696095A (de)
EP (1) EP0239384B1 (de)
JP (1) JPS62232142A (de)
AT (1) ATE187845T1 (de)
DE (1) DE3752303D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6362272A (ja) * 1986-09-02 1988-03-18 Seiko Instr & Electronics Ltd 半導体装置の製造方法
GB8905511D0 (en) * 1989-03-10 1989-04-19 British Telecomm Preparing substrates
US4948456A (en) * 1989-06-09 1990-08-14 Delco Electronics Corporation Confined lateral selective epitaxial growth
WO1996017379A1 (en) * 1994-11-28 1996-06-06 Advanced Micro Devices, Inc. A method and system for providing an integrated circuit device that allows for a high field threshold voltage utilizing oxide spacers
US5907768A (en) * 1996-08-16 1999-05-25 Kobe Steel Usa Inc. Methods for fabricating microelectronic structures including semiconductor islands
US5930644A (en) * 1997-07-23 1999-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a shallow trench isolation using oxide slope etching
US8501566B1 (en) * 2012-09-11 2013-08-06 Nanya Technology Corp. Method for fabricating a recessed channel access transistor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4271583A (en) * 1980-03-10 1981-06-09 Bell Telephone Laboratories, Incorporated Fabrication of semiconductor devices having planar recessed oxide isolation region
JPS5760851A (en) * 1980-09-17 1982-04-13 Hitachi Ltd Dielectric isolation of semiconductor integrated circuit
JPS58134443A (ja) * 1982-02-04 1983-08-10 Toshiba Corp 半導体装置の製造方法
JPS5984435A (ja) * 1982-11-04 1984-05-16 Matsushita Electric Ind Co Ltd 半導体集積回路及びその製造方法

Also Published As

Publication number Publication date
JPS62232142A (ja) 1987-10-12
EP0239384A3 (de) 1992-01-22
EP0239384B1 (de) 1999-12-15
EP0239384A2 (de) 1987-09-30
DE3752303D1 (de) 2000-01-20
US4696095A (en) 1987-09-29

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties