ATE182229T1 - Multi-bit blockweises schreiben in einem dynamischen direktzugriffsspeicher - Google Patents

Multi-bit blockweises schreiben in einem dynamischen direktzugriffsspeicher

Info

Publication number
ATE182229T1
ATE182229T1 AT96913990T AT96913990T ATE182229T1 AT E182229 T1 ATE182229 T1 AT E182229T1 AT 96913990 T AT96913990 T AT 96913990T AT 96913990 T AT96913990 T AT 96913990T AT E182229 T1 ATE182229 T1 AT E182229T1
Authority
AT
Austria
Prior art keywords
write register
bit
blockwise
write
random access
Prior art date
Application number
AT96913990T
Other languages
English (en)
Inventor
Loren L Mclaury
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE182229T1 publication Critical patent/ATE182229T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G11C7/1033—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
AT96913990T 1995-05-11 1996-05-10 Multi-bit blockweises schreiben in einem dynamischen direktzugriffsspeicher ATE182229T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/439,358 US5559749A (en) 1995-05-11 1995-05-11 Multi-bit block write in a random access memory

Publications (1)

Publication Number Publication Date
ATE182229T1 true ATE182229T1 (de) 1999-07-15

Family

ID=23744398

Family Applications (1)

Application Number Title Priority Date Filing Date
AT96913990T ATE182229T1 (de) 1995-05-11 1996-05-10 Multi-bit blockweises schreiben in einem dynamischen direktzugriffsspeicher

Country Status (8)

Country Link
US (2) US5559749A (de)
EP (1) EP0826216B1 (de)
JP (1) JP4032102B2 (de)
KR (1) KR100306015B1 (de)
AT (1) ATE182229T1 (de)
AU (1) AU5679196A (de)
DE (1) DE69603275T2 (de)
WO (1) WO1996036052A2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08212132A (ja) * 1995-02-07 1996-08-20 Mitsubishi Electric Corp 記憶装置
US5657289A (en) * 1995-08-30 1997-08-12 Micron Technology, Inc. Expandable data width SAM for a multiport RAM
US6011727A (en) * 1998-08-26 2000-01-04 Micron Technology, Inc. Block write circuit and method for wide data path memory devices
US6445641B1 (en) * 1999-09-02 2002-09-03 G-Link Technology Memory device with time shared data lines
US6256253B1 (en) 2000-02-18 2001-07-03 Infineon Technologies North America Corp. Memory device with support for unaligned access
KR100855861B1 (ko) * 2005-12-30 2008-09-01 주식회사 하이닉스반도체 비휘발성 반도체 메모리 장치
KR101796116B1 (ko) 2010-10-20 2017-11-10 삼성전자 주식회사 반도체 장치, 이를 포함하는 메모리 모듈, 메모리 시스템 및 그 동작방법
US11581035B2 (en) * 2021-02-24 2023-02-14 Micron Technology, Inc. Systems, devices, and methods for efficient usage of IO section breaks in memory devices

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3884859T2 (de) * 1987-06-04 1994-02-03 Nippon Electric Co Dynamische Speicherschaltung mit einem Abfühlschema.
US4807189A (en) * 1987-08-05 1989-02-21 Texas Instruments Incorporated Read/write memory having a multiple column select mode
US4891794A (en) * 1988-06-20 1990-01-02 Micron Technology, Inc. Three port random access memory
US5235545A (en) * 1991-03-29 1993-08-10 Micron Technology, Inc. Memory array write addressing circuit for simultaneously addressing selected adjacent memory cells
US5282177A (en) * 1992-04-08 1994-01-25 Micron Technology, Inc. Multiple register block write method and circuit for video DRAMs
US5311478A (en) * 1992-08-18 1994-05-10 Micron Technology, Inc. Integrated circuit memory with asymmetric row access topology
US5323350A (en) * 1992-08-18 1994-06-21 Micron Technologies, Inc. Integrated circuit memory with dual P-sense amplifiers associated with each column line
US5394172A (en) * 1993-03-11 1995-02-28 Micron Semiconductor, Inc. VRAM having isolated array sections for providing write functions that will not affect other array sections
JPH09506439A (ja) * 1993-10-29 1997-06-24 サン・マイクロシステムズ・インコーポレーテッド 行アドレス・ストローブ・サイクルを必要としないでフレーム・バッファ動作を行う方法と装置
US5504855A (en) * 1993-10-29 1996-04-02 Sun Microsystems, Inc. Method and apparatus for providing fast multi-color storage in a frame buffer

Also Published As

Publication number Publication date
EP0826216B1 (de) 1999-07-14
DE69603275T2 (de) 1999-11-04
US6021084A (en) 2000-02-01
JPH10513596A (ja) 1998-12-22
DE69603275D1 (de) 1999-08-19
US5559749A (en) 1996-09-24
WO1996036052A2 (en) 1996-11-14
EP0826216A2 (de) 1998-03-04
KR100306015B1 (ko) 2001-11-15
AU5679196A (en) 1996-11-29
WO1996036052A3 (en) 1997-01-09
KR19990014668A (ko) 1999-02-25
JP4032102B2 (ja) 2008-01-16

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Legal Events

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