ATE145305T1 - Programmierbare logische vorrichtung - Google Patents

Programmierbare logische vorrichtung

Info

Publication number
ATE145305T1
ATE145305T1 AT91303771T AT91303771T ATE145305T1 AT E145305 T1 ATE145305 T1 AT E145305T1 AT 91303771 T AT91303771 T AT 91303771T AT 91303771 T AT91303771 T AT 91303771T AT E145305 T1 ATE145305 T1 AT E145305T1
Authority
AT
Austria
Prior art keywords
logic circuit
programmable logic
delay line
inputs
programmable
Prior art date
Application number
AT91303771T
Other languages
English (en)
Inventor
Robert D Norman
Sai-Keung Lee
Om P Agrawal
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE145305T1 publication Critical patent/ATE145305T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
    • H03K5/1504—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a chain of active delay devices

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Pulse Circuits (AREA)
AT91303771T 1990-04-30 1991-04-25 Programmierbare logische vorrichtung ATE145305T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US51675290A 1990-04-30 1990-04-30

Publications (1)

Publication Number Publication Date
ATE145305T1 true ATE145305T1 (de) 1996-11-15

Family

ID=24056946

Family Applications (1)

Application Number Title Priority Date Filing Date
AT91303771T ATE145305T1 (de) 1990-04-30 1991-04-25 Programmierbare logische vorrichtung

Country Status (4)

Country Link
EP (1) EP0455428B1 (de)
JP (1) JPH04229720A (de)
AT (1) ATE145305T1 (de)
DE (1) DE69123077D1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6697957B1 (en) * 2000-05-11 2004-02-24 Quickturn Design Systems, Inc. Emulation circuit with a hold time algorithm, logic analyzer and shadow memory
US8629691B2 (en) * 2011-05-17 2014-01-14 Altera Corporation Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1201410B (de) * 1963-04-04 1965-09-23 Olympia Werke Ag Verfahren und Vorrichtung zur Verzoegerung von Impulsfolgen
US3987410A (en) * 1974-06-24 1976-10-19 International Business Machines Corporation Array logic fabrication for use in pattern recognition equipments and the like
JPS60219675A (ja) * 1984-04-13 1985-11-02 Sony Corp 時間軸変換回路
US4691302A (en) * 1985-09-04 1987-09-01 Siemens Aktiengesellschaft Circuit arrangement comprising a matrix-shaped memory arrangement for variably adjustable delay of digital signals
US4746823A (en) * 1986-07-02 1988-05-24 Dallas Semiconductor Corporation Voltage-insensitive and temperature-compensated delay circuit for a monolithic integrated circuit
EP0653842A3 (de) * 1988-12-16 1995-05-31 Advanced Micro Devices, Inc. Steuerlogik zur Auswahl der Polarität

Also Published As

Publication number Publication date
JPH04229720A (ja) 1992-08-19
DE69123077D1 (de) 1996-12-19
EP0455428B1 (de) 1996-11-13
EP0455428A3 (en) 1993-02-24
EP0455428A2 (de) 1991-11-06

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties