ATA994272A - Verfahren zur herstellung einer halbleiteranordnung mit wenigstens einem feldeffekttransistor mit mindestens einer isolierten torelektrode - Google Patents

Verfahren zur herstellung einer halbleiteranordnung mit wenigstens einem feldeffekttransistor mit mindestens einer isolierten torelektrode

Info

Publication number
ATA994272A
ATA994272A AT994272A AT994272A ATA994272A AT A994272 A ATA994272 A AT A994272A AT 994272 A AT994272 A AT 994272A AT 994272 A AT994272 A AT 994272A AT A994272 A ATA994272 A AT A994272A
Authority
AT
Austria
Prior art keywords
producing
gate electrode
field effect
effect transistor
insulated gate
Prior art date
Application number
AT994272A
Other languages
German (de)
English (en)
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of ATA994272A publication Critical patent/ATA994272A/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/1055Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components comprising charge coupled devices of the so-called bucket brigade type
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10Regulating voltage or current
    • G05F1/12Regulating voltage or current wherein the variable actually regulated by the final control device is ac
    • G05F1/24Regulating voltage or current wherein the variable actually regulated by the final control device is ac using bucking or boosting transformers as final control devices
    • G05F1/247Regulating voltage or current wherein the variable actually regulated by the final control device is ac using bucking or boosting transformers as final control devices with motor in control circuit
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electromagnetism (AREA)
  • Automation & Control Theory (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)
AT994272A 1971-11-25 1972-11-22 Verfahren zur herstellung einer halbleiteranordnung mit wenigstens einem feldeffekttransistor mit mindestens einer isolierten torelektrode ATA994272A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7116182A NL7116182A (es) 1971-11-25 1971-11-25

Publications (1)

Publication Number Publication Date
ATA994272A true ATA994272A (de) 1975-08-15

Family

ID=19814543

Family Applications (1)

Application Number Title Priority Date Filing Date
AT994272A ATA994272A (de) 1971-11-25 1972-11-22 Verfahren zur herstellung einer halbleiteranordnung mit wenigstens einem feldeffekttransistor mit mindestens einer isolierten torelektrode

Country Status (11)

Country Link
JP (1) JPS4861078A (es)
AR (1) AR194520A1 (es)
AT (1) ATA994272A (es)
AU (1) AU469642B2 (es)
CA (1) CA970077A (es)
DE (1) DE2254821A1 (es)
ES (1) ES408908A1 (es)
FR (1) FR2161003B1 (es)
GB (1) GB1409095A (es)
IT (1) IT975824B (es)
NL (1) NL7116182A (es)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4142199A (en) * 1977-06-24 1979-02-27 International Business Machines Corporation Bucket brigade device and process
JPS5534493A (en) * 1978-08-31 1980-03-11 Ibm Bucket brigade cell

Also Published As

Publication number Publication date
ES408908A1 (es) 1975-10-16
GB1409095A (en) 1975-10-08
CA970077A (en) 1975-06-24
DE2254821A1 (de) 1973-05-30
AR194520A1 (es) 1973-07-23
NL7116182A (es) 1973-05-29
JPS4861078A (es) 1973-08-27
FR2161003B1 (es) 1978-02-03
IT975824B (it) 1974-08-10
FR2161003A1 (es) 1973-07-06
AU469642B2 (en) 1976-02-19
AU4908072A (en) 1974-05-23

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