AT329114B - Halbleiteranordnung, insbesondere monolithische integrierte schaltung, mit voneinander isolierten halbleiterinseln - Google Patents

Halbleiteranordnung, insbesondere monolithische integrierte schaltung, mit voneinander isolierten halbleiterinseln

Info

Publication number
AT329114B
AT329114B AT593771A AT593771A AT329114B AT 329114 B AT329114 B AT 329114B AT 593771 A AT593771 A AT 593771A AT 593771 A AT593771 A AT 593771A AT 329114 B AT329114 B AT 329114B
Authority
AT
Austria
Prior art keywords
semi
conductor
integrated circuit
monolithic integrated
particular monolithic
Prior art date
Application number
AT593771A
Other languages
German (de)
English (en)
Other versions
ATA593771A (de
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of ATA593771A publication Critical patent/ATA593771A/de
Application granted granted Critical
Publication of AT329114B publication Critical patent/AT329114B/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H10D84/403—Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
    • H10D84/615—Combinations of vertical BJTs and one or more of resistors or capacitors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/145—Shaped junctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
AT593771A 1970-07-10 1971-07-08 Halbleiteranordnung, insbesondere monolithische integrierte schaltung, mit voneinander isolierten halbleiterinseln AT329114B (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NLAANVRAGE7010205,A NL169936C (nl) 1970-07-10 1970-07-10 Halfgeleiderinrichting omvattende een halfgeleiderlichaam met een althans ten dele in het halfgeleiderlichaam verzonken oxydepatroon.

Publications (2)

Publication Number Publication Date
ATA593771A ATA593771A (de) 1975-07-15
AT329114B true AT329114B (de) 1976-04-26

Family

ID=19810545

Family Applications (2)

Application Number Title Priority Date Filing Date
AT593771A AT329114B (de) 1970-07-10 1971-07-08 Halbleiteranordnung, insbesondere monolithische integrierte schaltung, mit voneinander isolierten halbleiterinseln
AT593871A AT329115B (de) 1970-07-10 1971-07-08 Halbleiteranordnung mit versenktem isoliermuster und an dieses grenzender dotierter zone

Family Applications After (1)

Application Number Title Priority Date Filing Date
AT593871A AT329115B (de) 1970-07-10 1971-07-08 Halbleiteranordnung mit versenktem isoliermuster und an dieses grenzender dotierter zone

Country Status (13)

Country Link
US (1) US3718843A (cg-RX-API-DMAC7.html)
JP (1) JPS5029629B1 (cg-RX-API-DMAC7.html)
AT (2) AT329114B (cg-RX-API-DMAC7.html)
BE (1) BE769730A (cg-RX-API-DMAC7.html)
CA (1) CA927015A (cg-RX-API-DMAC7.html)
CH (1) CH528823A (cg-RX-API-DMAC7.html)
DE (1) DE2133977C3 (cg-RX-API-DMAC7.html)
ES (1) ES393036A1 (cg-RX-API-DMAC7.html)
FR (1) FR2098320B1 (cg-RX-API-DMAC7.html)
GB (1) GB1353488A (cg-RX-API-DMAC7.html)
NL (1) NL169936C (cg-RX-API-DMAC7.html)
SE (1) SE368482B (cg-RX-API-DMAC7.html)
ZA (2) ZA714522B (cg-RX-API-DMAC7.html)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL170901C (nl) * 1971-04-03 1983-01-03 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
NL166156C (nl) * 1971-05-22 1981-06-15 Philips Nv Halfgeleiderinrichting bevattende ten minste een op een halfgeleidersubstraatlichaam aangebrachte halfge- leiderlaag met ten minste een isolatiezone, welke een in de halfgeleiderlaag verzonken isolatielaag uit door plaatselijke thermische oxydatie van het half- geleidermateriaal van de halfgeleiderlaag gevormd isolerend materiaal bevat en een werkwijze voor het vervaardigen daarvan.
GB1393027A (en) * 1972-05-30 1975-05-07 Ferranti Ltd Semiconductor devices
JPS5228550B2 (cg-RX-API-DMAC7.html) * 1972-10-04 1977-07-27

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US34420A (en) * 1862-02-18 Improvement in tools
FR1458860A (fr) * 1964-12-24 1966-03-04 Ibm Dispositif à circuit intégré, utilisant une lamelle semi-conductrice pré-formée
US3386865A (en) * 1965-05-10 1968-06-04 Ibm Process of making planar semiconductor devices isolated by encapsulating oxide filled channels
US3597287A (en) * 1965-11-16 1971-08-03 Monsanto Co Low capacitance field effect transistor
FR1527898A (fr) * 1967-03-16 1968-06-07 Radiotechnique Coprim Rtc Agencement de dispositifs semi-conducteurs portés par un support commun et son procédé de fabrication

Also Published As

Publication number Publication date
AT329115B (de) 1976-04-26
GB1353488A (en) 1974-05-15
CA927015A (en) 1973-05-22
FR2098320B1 (cg-RX-API-DMAC7.html) 1974-10-11
ZA714523B (en) 1973-02-28
FR2098320A1 (cg-RX-API-DMAC7.html) 1972-03-10
ATA593871A (de) 1975-07-15
BE769730A (fr) 1972-01-10
DE2133977B2 (de) 1978-12-21
JPS5029629B1 (cg-RX-API-DMAC7.html) 1975-09-25
NL169936B (nl) 1982-04-01
ES393036A1 (es) 1973-08-16
US3718843A (en) 1973-02-27
DE2133977C3 (de) 1979-08-30
ZA714522B (en) 1973-02-28
CH528823A (de) 1972-09-30
NL7010205A (cg-RX-API-DMAC7.html) 1972-01-12
ATA593771A (de) 1975-07-15
SE368482B (cg-RX-API-DMAC7.html) 1974-07-01
DE2133977A1 (de) 1972-01-13
NL169936C (nl) 1982-09-01

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Legal Events

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ELJ Ceased due to non-payment of the annual fee