GB1393027A - Semiconductor devices - Google Patents

Semiconductor devices

Info

Publication number
GB1393027A
GB1393027A GB2516872A GB2516872A GB1393027A GB 1393027 A GB1393027 A GB 1393027A GB 2516872 A GB2516872 A GB 2516872A GB 2516872 A GB2516872 A GB 2516872A GB 1393027 A GB1393027 A GB 1393027A
Authority
GB
United Kingdom
Prior art keywords
layer
tracks
diffusion
type
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2516872A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ferranti International PLC
Original Assignee
Ferranti PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ferranti PLC filed Critical Ferranti PLC
Priority to GB2516872A priority Critical patent/GB1393027A/en
Priority to DE19732324554 priority patent/DE2324554A1/en
Priority to AR24827173A priority patent/AR199106A1/en
Priority to BR400173A priority patent/BR7304001D0/en
Priority to JP5990073A priority patent/JPS4962091A/ja
Priority to US05/542,674 priority patent/US3945032A/en
Publication of GB1393027A publication Critical patent/GB1393027A/en
Priority to US05/634,277 priority patent/US4053336A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/09—Resistor-transistor logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

1393027 Integrated circuits FERRANTI Ltd 17 May 1973 [30 May 1972] 25168/72 Heading H1K A network of N type conductive tracks 24 is formed by diffusion into an epitaxial P-type semi-conductor layer 14 on a P-type substrate 13 constituting a conductive plane, unmodified regions 18, 14<SP>1</SP> of the layer 14 being left to form portions of circuit elements and to provide means for gaining electrical access to the substrate 13 from the upper surface 27. A desired integrated circuit configuration is then obtained by forming a metallization pattern by the selective removal of metal from an initially continuous layer, preferably deposited over an apertured oxide coating 26. Particularly described is an array of Si NOR gates each of which includes two NPN collector-diffusion-isolated bipolar transistors 11, 12 as well as other elements such as resistors, diodes and PN junction FETs. The N<SP>+</SP> conductive tracks 24 form a matrix of intersecting tracks, with the circuit components forming the gates located in the interstices of the matrix. As shown the collector region 15 of one of the transistors 12 is contiguous with one of the tracks 24, the emitter region 19 of the other transistor being connected to the substrate conductive plane 13 through a portion 14<SP>1</SP> of the epitaxial layer 14. Optionally the layer 14 may be subjected to a non-selective diffusion to form a P<SP>+</SP> type surface layer. Instead of the simple A1 metallization pattern shown a multilayer metallization system may be used. Another embodiment (Fig. 5, not shown) includes a bipolar transistor (50) laterally isolated by an inset oxide barrier (54) formed by oxidation of the epitaxial layer (52) within a groove etched around the transistor.
GB2516872A 1972-05-30 1972-05-30 Semiconductor devices Expired GB1393027A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
GB2516872A GB1393027A (en) 1972-05-30 1972-05-30 Semiconductor devices
DE19732324554 DE2324554A1 (en) 1972-05-30 1973-05-15 Semiconductor device and process for its production
AR24827173A AR199106A1 (en) 1972-05-30 1973-05-29 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
BR400173A BR7304001D0 (en) 1972-05-30 1973-05-29 A SEMICONDUCTOR APPLIANCE AND ITS MANUFACTURING PROCESS
JP5990073A JPS4962091A (en) 1972-05-30 1973-05-30
US05/542,674 US3945032A (en) 1972-05-30 1975-01-21 Semiconductor integrated circuit device having a conductive plane and a diffused network of conductive tracks
US05/634,277 US4053336A (en) 1972-05-30 1975-11-21 Method of manufacturing a semiconductor integrated circuit device having a conductive plane and a diffused network of conductive tracks

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2516872A GB1393027A (en) 1972-05-30 1972-05-30 Semiconductor devices

Publications (1)

Publication Number Publication Date
GB1393027A true GB1393027A (en) 1975-05-07

Family

ID=10223324

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2516872A Expired GB1393027A (en) 1972-05-30 1972-05-30 Semiconductor devices

Country Status (5)

Country Link
JP (1) JPS4962091A (en)
AR (1) AR199106A1 (en)
BR (1) BR7304001D0 (en)
DE (1) DE2324554A1 (en)
GB (1) GB1393027A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2134596A (en) * 1983-02-04 1984-08-15 Fev Forsch Energietech Verbr Fresh charge intake quantity control in an internal combustion engine

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR155459A (en) * 1967-01-23
US3538397A (en) * 1967-05-09 1970-11-03 Motorola Inc Distributed semiconductor power supplies and decoupling capacitor therefor
NL169936C (en) * 1970-07-10 1982-09-01 Philips Nv SEMI-CONDUCTOR DEVICE CONTAINING A SEMI-CONDUCTOR BODY WITH AN OXYDE PATTERN SATURATED AT LEAST IN PART IN THE SEMI-CONDUCTOR BODY.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2134596A (en) * 1983-02-04 1984-08-15 Fev Forsch Energietech Verbr Fresh charge intake quantity control in an internal combustion engine

Also Published As

Publication number Publication date
DE2324554A1 (en) 1973-12-13
AR199106A1 (en) 1974-08-08
DE2324554C2 (en) 1987-08-13
JPS4962091A (en) 1974-06-15
BR7304001D0 (en) 1974-07-11

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Legal Events

Date Code Title Description
PS Patent sealed
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
PE20 Patent expired after termination of 20 years

Effective date: 19930516