AT264596B - Verfahren zum Herstellen eines Transistors - Google Patents
Verfahren zum Herstellen eines TransistorsInfo
- Publication number
- AT264596B AT264596B AT68567A AT68567A AT264596B AT 264596 B AT264596 B AT 264596B AT 68567 A AT68567 A AT 68567A AT 68567 A AT68567 A AT 68567A AT 264596 B AT264596 B AT 264596B
- Authority
- AT
- Austria
- Prior art keywords
- transistor
- manufacturing
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/05—Etch and refill
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/106—Masks, special
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DES0101632 | 1966-01-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AT264596B true AT264596B (de) | 1968-09-10 |
Family
ID=7523884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT68567A AT264596B (de) | 1966-01-26 | 1967-01-24 | Verfahren zum Herstellen eines Transistors |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US3551220A (de) |
| AT (1) | AT264596B (de) |
| CH (1) | CH457626A (de) |
| DE (1) | DE1514673A1 (de) |
| FR (1) | FR1513645A (de) |
| GB (1) | GB1137372A (de) |
| NL (1) | NL6615034A (de) |
| SE (1) | SE339052B (de) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3895978A (en) * | 1969-08-12 | 1975-07-22 | Kogyo Gijutsuin | Method of manufacturing transistors |
| US3678573A (en) * | 1970-03-10 | 1972-07-25 | Westinghouse Electric Corp | Self-aligned gate field effect transistor and method of preparing |
| US3764865A (en) * | 1970-03-17 | 1973-10-09 | Rca Corp | Semiconductor devices having closely spaced contacts |
| DE2120388A1 (de) * | 1970-04-28 | 1971-12-16 | Agency Ind Science Techn | Verbindungshalbleitervorrichtung |
| US3675313A (en) * | 1970-10-01 | 1972-07-11 | Westinghouse Electric Corp | Process for producing self aligned gate field effect transistor |
| US3713909A (en) * | 1970-11-06 | 1973-01-30 | North American Rockwell | Method of producing a tunnel diode |
| US4677456A (en) * | 1979-05-25 | 1987-06-30 | Raytheon Company | Semiconductor structure and manufacturing method |
| US4535531A (en) * | 1982-03-22 | 1985-08-20 | International Business Machines Corporation | Method and resulting structure for selective multiple base width transistor structures |
| US4435898A (en) | 1982-03-22 | 1984-03-13 | International Business Machines Corporation | Method for making a base etched transistor integrated circuit |
| US4954455A (en) * | 1984-12-18 | 1990-09-04 | Advanced Micro Devices | Semiconductor memory device having protection against alpha strike induced errors |
-
1966
- 1966-01-26 DE DE19661514673 patent/DE1514673A1/de active Pending
- 1966-10-24 NL NL6615034A patent/NL6615034A/xx unknown
-
1967
- 1967-01-23 US US611010A patent/US3551220A/en not_active Expired - Lifetime
- 1967-01-24 FR FR92263A patent/FR1513645A/fr not_active Expired
- 1967-01-24 AT AT68567A patent/AT264596B/de active
- 1967-01-24 SE SE01047/67A patent/SE339052B/xx unknown
- 1967-01-24 CH CH102467A patent/CH457626A/de unknown
- 1967-01-25 GB GB3703/67A patent/GB1137372A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US3551220A (en) | 1970-12-29 |
| GB1137372A (en) | 1968-12-18 |
| CH457626A (de) | 1968-06-15 |
| DE1514673A1 (de) | 1969-06-19 |
| FR1513645A (fr) | 1968-02-16 |
| SE339052B (de) | 1971-09-27 |
| NL6615034A (de) | 1967-07-27 |
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