CH481489A - Verfahren zur Herstellung eines Transistors - Google Patents

Verfahren zur Herstellung eines Transistors

Info

Publication number
CH481489A
CH481489A CH121966A CH121966A CH481489A CH 481489 A CH481489 A CH 481489A CH 121966 A CH121966 A CH 121966A CH 121966 A CH121966 A CH 121966A CH 481489 A CH481489 A CH 481489A
Authority
CH
Switzerland
Prior art keywords
transistor
manufacturing
Prior art date
Application number
CH121966A
Other languages
English (en)
Inventor
Cullis Roger
Original Assignee
Itt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Itt filed Critical Itt
Publication of CH481489A publication Critical patent/CH481489A/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/04—Dopants, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/041—Doping control in crystal growth
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/157—Special diffusion and profiles
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/965—Shaped junction formation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
CH121966A 1965-02-01 1966-01-28 Verfahren zur Herstellung eines Transistors CH481489A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB4290/65A GB1028485A (en) 1965-02-01 1965-02-01 Semiconductor devices

Publications (1)

Publication Number Publication Date
CH481489A true CH481489A (de) 1969-11-15

Family

ID=9774366

Family Applications (1)

Application Number Title Priority Date Filing Date
CH121966A CH481489A (de) 1965-02-01 1966-01-28 Verfahren zur Herstellung eines Transistors

Country Status (6)

Country Link
US (1) US3473975A (de)
BE (1) BE675856A (de)
CH (1) CH481489A (de)
DE (1) DE1564110A1 (de)
GB (1) GB1028485A (de)
NL (1) NL6601231A (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1764398B1 (de) * 1968-05-30 1971-02-04 Itt Ind Gmbh Deutsche Sperrschichtkondensator
US4225874A (en) * 1978-03-09 1980-09-30 Rca Corporation Semiconductor device having integrated diode
US5091321A (en) * 1991-07-22 1992-02-25 Allegro Microsystems, Inc. Method for making an NPN transistor with controlled base width compatible with making a Bi-MOS integrated circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL297002A (de) * 1962-08-23 1900-01-01
NL297288A (de) * 1962-08-31
DE1229650B (de) * 1963-09-30 1966-12-01 Siemens Ag Verfahren zum Herstellen eines Halbleiter-bauelementes mit pn-UEbergang nach der Planar-Diffusionstechnik
US3370995A (en) * 1965-08-02 1968-02-27 Texas Instruments Inc Method for fabricating electrically isolated semiconductor devices in integrated circuits

Also Published As

Publication number Publication date
NL6601231A (de) 1966-08-02
US3473975A (en) 1969-10-21
BE675856A (de) 1966-08-01
DE1564110A1 (de) 1970-01-15
GB1028485A (en) 1966-05-04

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Legal Events

Date Code Title Description
PL Patent ceased